In January this year, NVIDIA announced that SiFive, a U.S.-based RISC-V IP core company, has joined its core ecosystem, enabling RISC-V processors to achieve high-speed coherent interconnection with NVIDIA chips via NVLink. Three months later, NVIDIA further participated in SiFive's $400 million Series G funding round. The path of integrated development between open instruction sets and AI computing is gradually unfolding in 2026.
The Path of Standard Evolution from MCU to Intelligent Computing
From the perspective of open instruction set standard development, the release of two key technical specifications—2021 Vector Extension Specification 1.0 (RVV 1.0) and 2024 High-Performance Profile Specification (RVA23 Profile)—divides the evolution of the RISC-V industry into three stages.
Three Stages of RISC-V Industry Evolution
Stage 1 (2015-2021): Establishing a Foothold in the MCU Field.
From the launch of the RISC-V project at the University of California, Berkeley in 2010, to the establishment of RISC-V International in 2015, early RISC-V rapidly penetrated embedded scenarios primarily relying on its advantages of being open-source, royalty-free, modular, and customizable. However, the RISC-V technical specifications during this period lacked native support for vector and parallel computing, making it difficult for RISC-V to enter high-performance computing scenarios.
At the end of 2021, RISC-V International officially released RVV 1.0, adding over a hundred instructions. This provided vector-accelerated computing capabilities for data-intensive fields such as cryptography, signal processing, and AI computing, marking RISC-V's first step from embedded systems to high-performance computing.
Stage 2 (2022-2025): Extending to Automotive Electronics and High-Performance Computing.
Relying on the parallel computing capabilities brought by the RVV specification, the RISC-V industry has developed rapidly on a global scale. Domestic enterprises such as Alibaba DAMO Academy, Beijing Open Source Chip Research Institute, Nuclei System Technology, and international companies like SiFive have all quickly launched new-generation IP cores integrating vector units, achieving initial commercial deployment of vector extensions in automotive electronics and edge computing.
However, during the expansion of applications in the high-performance computing field, the industry faced issues of diverse implementation methods caused by inconsistent specifications, which in turn led to difficulties in software compatibility and adaptation. Defining a set of specification combinations (profiles) jointly followed by RISC-V vendors based on applications is the solution proposed by RISC-V International. In April 2023, the first batch of Profile specifications was officially released (including three specifications: RVA20, RVI20, and RVA22), but this batch of profiles still provided incomplete support for high-performance computing, and key features such as virtualization were not yet ready.
RISC-V International Officially Approves the RVA23 Profile (Source: RISC-V International Official Website)
In October 2024, RISC-V International officially approved the RVA23 Profile—making vector and virtualization extensions mandatory for the first time, defining a complete feature set for high-performance computing for RISC-V. Open-source software stacks such as the global Linux community have begun adapting to the RVA23 standard. From operating systems and compilers to AI frameworks, RISC-V now has a unified, portable software target platform geared towards high-performance scenarios.
Stage 3 (2025-Present): Advancing into High-Performance and AI Inference Computing.
Following the release of the RVA23 Profile specification, the industrialization process of RISC-V in high-performance computing and AI has suddenly accelerated. RISC-V chip manufacturers have launched projects compliant with the RVA23 specification one after another. Domestic manufacturers such as SpacemiT and Lanxin Computing released the first batch of chip products based on RVA23 at the beginning of this year. Various Linux kernel communities and distribution communities are also actively promoting adaptation to the new specification.
Currently, on the basis of continuing to improve the RVA23.1 specification, RISC-V International plans to spend one to two years completing the formulation of the new matrix extension instruction set to enhance RISC-V's computing performance in the AI field. Three parallel technical routes have currently been formed. In industrial practice, some chip products have taken the lead in exploration. Alibaba DAMO Academy, Zhihe Computing, and SimAI have implemented matrix extension functions in actual chip products, and the industry has strong confidence in standardized implementation.
Currently, driven by key architecture standards, RISC-V has completed the industrial evolution of the open computing architecture from "embedded computing" to "a new pole of computing power," possessing the fundamental conditions to build a complete AI computing power foundation.
Three Core Modules for RISC-V to Build the AI Computing Power Foundation
From the perspective of industry trends, edge-side inference scenarios are the best entry point for RISC-V in the AI field. Vector extension, matrix acceleration, and heterogeneous integration capabilities are the three core modules for building an open, flexible, and low-cost computing power platform based on the RISC-V instruction set.
First, Vector Extension—Coping with Rapidly Changing Operator Libraries. As the number of non-linear operators in AI operator libraries increases, the industry's requirements for CPU computing capabilities continue to rise. From 2017 to the present, every generation of Transformer model innovation has introduced new operators—irregular data flows and complex control logic are common characteristics of these new operators. Coupled with the popularity of Agent computing loads, such computing tasks, which are more suitable for CPU execution, gradually account for 30% to 40% of inference time.
Softmax Operator Acceleration Effect
From the perspective of architecture design, this is also the advantage of the RISC-V vector extension. RVV 1.0 has built-in features such as reduction primitives and variable vector length from the very beginning of its design. The computational characteristics of operators like Softmax and RoPE can be efficiently implemented through RVV extension primitives, reducing the number of times data is transferred back and forth between the CPU and AI acceleration units. According to actual measurement data of the RISC-V vector extension, on the BERT-Large workload, when vector extensions are combined with AI custom extensions, the Softmax operator can be accelerated by 4.9 times.
Second, Matrix Extension—Architectural Evolution from Vector to Matrix. AI computing cannot bypass matrix multiplication. The two mainstream architectures, x86 and Arm, expanded matrix acceleration into their systems almost at the same time. Arm released the SME extension in 2021 and launched the mobile-oriented SME2 extension in 2025; Intel also introduced the AMX extension on server chips. By adding matrix extension instructions, both companies have further fortified their ecosystem moats.
Three Technical Routes for Matrix Extension
In addition, RISC-V is developing three parallel technical routes, building a matrix extension specification system that covers all computing power levels. Among them, the Integrated Matrix Extension (IME) reuses existing vector registers, targeting low-power embedded scenarios with minimal hardware overhead; the Vector Matrix Extension (VME) adds dedicated accumulators, targeting the mainstream market for inference chips; and the Attached Matrix Extension (AME) adopts a separate matrix register architecture, targeting high-computing-demand application scenarios. Currently, all three technical routes are being accelerated. In the future, the three will share a unified compilation path to avoid the fragmentation of the software ecosystem due to hardware divergence.
Proportion of Inference Time for Different Processors and Cores in Edge-Side AI Heterogeneous Computing Architecture
Third, Heterogeneous Integration—Open Paradigm for Edge-Side AI SoCs. The heterogeneous computing architecture of "dedicated AI chips/modules + vector-supported processors + control CPU cores" can maximize the coverage of different computing power application demands. Among them, dedicated accelerators target high-computing-power application scenarios, specializing in regular operations such as GEMM, covering 50% to 60% of inference time, and pursuing ultimate energy efficiency; vector processors handle some non-linear operators and main task loads, covering 30% to 40% of inference time; control CPU cores are responsible for control flow, task scheduling, and backing up long-tail operators.
The advantages of the RISC-V open instruction set can cover all links: the first layer of acceleration cores can achieve control-computation synergy through customized RISC-V instructions; the second layer is the native RISC-V vector extension; the third layer is the traditional RISC-V CPU core—using only the same set of open, royalty-free instruction sets, all three layers are fully integrated.
Currently, in the RISC-V camp, industrial practices based on the RVV standard specification and its extensions are also gradually being implemented. Products from companies such as Alibaba T-Head, HiSilicon, EVAS Intelligence, Sophgo, and Suzhou Ruixin cover inference demands from consumer terminals to data centers. Among them, EVAS Intelligence adopts a self-developed virtual instruction set based on RISC-V vector extensions for differentiated architecture innovation; Nanocorechip integrates RISC-V instruction set extensions with computing-in-memory accelerators. The further expansion of industrial practice will also promote the closed-loop convergence of standard specifications, thereby building a computing ecosystem for RISC-V in edge-side inference.
Ecosystem is the Core of the Computing Power Competition
The improvement of chip performance parameters completes half of the underlying application layout, but the ultimate focus of architecture competition is the ecosystem competition. Currently, the types of operators in edge-side inference scenarios are relatively controllable, and the vast majority of non-linear operators are more adaptable to RISC-V vector extensions, making the entry point for ecosystem construction relatively clear. The open nature of RISC-V provides a path completely different from closed ecosystems, enabling better collaborative construction of the entire ecosystem through industry-academia-research-application synergy.
Over the past two years since its establishment, the RISC-V Working Committee (hereinafter referred to as the "Working Committee"), under the guidance of the Ministry of Industry and Information Technology, has carried out a series of systematic layouts around AI ecosystem construction.
Standards First. The Working Committee officially released the RISC-V industry ecosystem standard system, covering five major fields: instruction sets, security and trustworthiness, basic software, testing and evaluation, and the industrial chain. On the basis of the international standards established by the RVA23 specification, the Working Committee further promotes the localized implementation of industry ecosystem standards, providing a rule foundation for the large-scale deployment of intelligent computing scenarios. At the recent high-performance platform symposium organized by the Working Committee, chip manufacturers reached a consensus that RISC-V has reached an ecosystem turning point in the data center field—mainstream operating systems, compilers, and AI frameworks have supported or plan to support RISC-V, and the application migration cost will significantly decrease after crossing this turning point.
Supplementing Shortcomings in the Software Stack. The Working Committee and the Institute of Software, Chinese Academy of Sciences co-built the "Ruyi Community" as a domestic hub for the RISC-V native software ecosystem, and jointly built the RISC-V native software stack with 24 industry-academia-research units, promoting the adaptation and optimization of over 100 software programs. Ruyi OS has been implemented on terminal devices such as AI tablets and AI PCs. At the AI framework level, the Institute of Software, Chinese Academy of Sciences has completed the adaptation of ROCm to the RISC-V architecture, bringing an order-of-magnitude improvement to large model inference performance.
Integration of Open Source and Openness Opens New Paths. The domestic open-source OpenHarmony community and the RISC-V open standard system are also accelerating their integration. SpacemiT and the Institute of Software, Chinese Academy of Sciences jointly released the RISC-V+OpenHarmony 5.0 native solution. The Shenzhen "OpenHarmony/RISC-V" Industry Alliance was officially established. The integrated innovation of open instruction set standards and open-source operating system foundations provides a full-stack open innovation path from chips to applications for China's information industry.
"RISC-V+AI" Initiates Large-Scale Tackling
The integration of RISC-V and AI is entering a "large-scale tackling" stage.
First, the matrix extension standard is still in the tackling period. Although the current parallel layout of three technical routes covers application scenarios across all computing power levels, the adaptation of the software stack always faces diversity challenges before the final release of international standards. How to collaborate within this time window is a key topic for all parties in the industry.
Second, ecosystem maturity is racing against other architectures. ARM is fortifying its mobile barriers with SME/SME2 matrix extensions. RISC-V needs to complete the leap from "usable" to "user-friendly" as soon as possible—the ultimate selection criteria for developers are delivery efficiency and total cost.
Third, the industrial collaboration mechanism under the open architecture still needs to be strengthened. The characteristic of RISC-V having no single commercial entity to back it is both an advantage and a challenge: the efficiency of upstream and downstream information transmission and joint research in chip design, software adaptation, and application implementation directly determines the speed of ecosystem construction.
From the perspective of the global industrial landscape, AI computing is opening new tracks in the fields of edge-side inference and dedicated computing. On these tracks, the flexibility and industrial collaboration capabilities of the open instruction set architecture are forming asymmetric competitive advantages relative to closed ecosystems.
For the domestic computing industry, RISC-V provides a new technical path that is not constrained by a single commercial entity and not locked into a closed ecosystem, while AI provides the broadest application prospects on this path. Currently, the integrated development of the two is also a historic opportunity for the restructuring of the domestic computing industry landscape. The RISC-V Working Committee will continue to focus on the three directions of standards, ecosystem, and industrial collaboration, uniting more industry-academia-research units to accelerate the adaptation and optimization of AI frameworks, inference engines, and key middleware, and further integrate the upstream and downstream collaboration chains of chip design, software adaptation, and terminal applications.
Author | Zhou Meng, Executive Secretary-General of the RISC-V Working Committee, China Electronics Standardization Association
Editor | Zhang Xinyi Art Editor | Ma Liya Supervisor | Lian Xiaodong