"Can RISC-V truly be put into practical use?" A few years ago, the answer to this question was often "It can run Linux now," "The processor has been taped out," or "Development boards are available." But in 2026, RISC-V has provided a new answer: real-world deployment of humanoid robots, mass production and installation of automotive-grade chips, and proactive adaptation of data center ecosystems—real scenarios are becoming the touchstone for RISC-V. As RISC-V enters more real-world scenarios, how to make the leap from "usable" to "user-friendly," enabling downstream customers to be "willing to use" and "proactively use" it, has become a new topic for the industry.
What Makes RISC-V "User-Friendly"?
If making RISC-V "usable" represents a breakthrough from "0 to 1," then making it "user-friendly" is the growth from "1 to N"—which not only entails richer connotations but also requires more fine-grained standards.
"The difference between 'usable' and 'user-friendly' is significant. 'Usable' usually means the system can boot, basic commands can run, and the desktop can be displayed; but 'user-friendly' means users and developers do not need to understand too many underlying differences, allowing them to seamlessly complete development, deployment, and application execution," Li Zhenning, Director of the openKylin Ecosystem Committee, told reporters from China Electronics News.
In Li Zhenning's view, for RISC-V to achieve a "user-friendly" status, at least five milestones must be met: first, the hardware platform's performance and stability must be sufficient to support real-world workloads; second, the toolchain, kernel, drivers, desktop environment, and software package repositories must form a stable version that developers can directly install and update; third, common development environments must be available, with GCC/LLVM, Python, Conda/Mamba, containers, debugging tools, and performance analysis tools functioning properly; fourth, key applications and industry frameworks must have native support, such as browsers, office suites, multimedia, AI (Artificial Intelligence) inference frameworks, and ROS; fifth, system installation, upgrades, issue feedback, documentation, and community support must be comprehensive enough for users to find solutions when encountering problems.
Another layer of connotation for "user-friendly" is finding and leveraging RISC-V's "killer feature" that distinguishes it from other instruction sets. Cao Changfeng, Chairman and CEO of Zijing Semiconductor, pointed out to reporters from China Electronics News that merely treating RISC-V as a drop-in replacement for the Arm architecture will fail to impress customers.
"When customers switch to or choose a specific chip architecture, they are invariably pursuing either a price advantage or a technical advantage. Compared to x86 and Arm, which have long achieved large-scale commercial shipment, RISC-V can achieve lower technical costs, but its commercial costs are high, putting it at a disadvantage in price competition, and there are also certain trial-and-error and learning costs. If it merely seeks to replace other instruction sets, customers will naturally have resistance," Cao Changfeng said. "For RISC-V companies, to enhance customer acceptance, they must address user pain points and meet users' new needs based on the unique advantages of RISC-V, so that users can have a sense of it being 'user-friendly'."
It is reported that during the definition and R&D of RISC-V automotive-grade chips, since the customers' vehicle models are mainly off-road vehicles, the Zijing team incorporated special instructions to enhance the chip's ESD (Electrostatic Discharge) protection capabilities. They also implemented edge AI functions using the RISC-V instruction set in next-generation products, creating differentiated capabilities leveraging the RISC-V architecture.
How Can RISC-V Expand Into More Application Scenarios?
When asked by reporters how to enable more scenarios and more users to adopt RISC-V, relevant practitioners repeatedly emphasized the word "real," such as real-machine environments, real businesses, and real scenarios. The logic behind this is simple and direct—good products are "used" into existence. With landing scenarios and customer feedback, RISC-V can become "increasingly user-friendly" and grow the depth of its ecosystem through collaborative adaptation across the industrial chain.
Scenario 1: Embodied Intelligent Robots: Cross-Domain Collaborative Adaptation in Real Scenarios
In May this year, a video circulated widely on social media among reporters. In the footage, a humanoid robot walks smoothly and fluently on a road between a green belt and an open-air parking lot, completing actions such as spinning in place. Compared to its "peers" that breakdance or perform martial arts, its movements seem rather ordinary, yet they convey a deep industrial signal—this is the first embodied AI humanoid robot powered by the openKylin operating system, marking the leap from technical adaptation to real-machine deployment for domestic open-source operating systems in the field of "RISC-V architecture humanoid robots."
It is reported that the adaptation plan for this RISC-V humanoid robot started in January 2026. The Kylin Software team and community partners jointly undertook the adaptation of the operating system base, ROS component integration, system stability verification, RISC-V AI software stack adaptation, and real-machine function joint debugging. After months of collaborative efforts, they achieved the stable operation of the openKylin operating system on the humanoid robot. "Embodied intelligent robots are different from ordinary development boards; they have higher requirements for real-time performance, stability, driver compatibility, motion control links, and perception-interaction links," Li Zhenning stated.
Through this practice, Kylin Software and the openKylin community have accumulated experience in several aspects: first, using real scenarios to guide adaptation, rather than staying at the preliminary stage of "the system can boot and basic functions are available," but instead facing the actual needs of RISC-V in different scenarios such as desktop office, edge computing, and robotics; second, strengthening cross-domain collaboration by uniting chip manufacturers, OEMs, operating systems, basic software, application software, testing and certification, and open-source communities to form an ecosystem pattern of collaborative innovation, continuous iteration, and joint development; third, attaching importance to step-by-step verification from simulation environments and development board environments to real-machine environments to reduce late-stage integration risks; fourth, depositing adaptation results back into the community as much as possible, including software packages, patches, documentation, and issue lists, to form reusable ecosystem capabilities.
Scenario 2: Automotive-Grade Semiconductors: Deep Underlying Collaboration to Pass 3,000 Tests
Automotive applications have always been regarded as one of the scenarios with the highest reliability requirements and the most stringent standards. In December 2025, Zijing Semiconductor released the world's first mass-produced and vehicle-installed RISC-V chip, the "Zijing M100." Cao Changfeng stated that RISC-V MCU (Microcontroller Unit) products such as the M100 have already begun shipping, with small-batch verification as the main focus this year, and large-scale shipments expected next year.
Looking back on the M100's journey to vehicle installation, continuous testing is the main thread of Cao Changfeng's memory. When asked how many tests the M100 underwent, his answer was: nearly 3,000.
Specifically, the Zijing team conducted over 800 tests at the chip level and passed automotive-grade certifications such as ISO 26262, A-SPICE, AEC-Q100, ISO 27001, and ISO/SAE 21434; at the software level, they completed tests for MCAL (Microcontroller Abstraction Layer), static code, and dynamic code; during the in-vehicle software adaptation stage, the team spent over a year with partners on hardware and software debugging, passing 1,430 tests at the controller level; at the whole-vehicle level, they passed several hundred more tests.
Through deep collaboration with IP suppliers, basic software suppliers, OEMs, and testing and standards institutions, Zijing Semiconductor has established a complete set of cooperation mechanisms in automotive-grade RISC-V and integrated relevant experience into the formulation of standards in fields such as RISC-V, automotive chips, and whole vehicles.
"We know there are 'two 10-year commitments' for automotive chips: the first is a decade of zero chip quality defects requiring massive testing and verification; the second is a decade of stable supply. It is recommended that RISC-V practitioners first bind with at least one alpha customer to enhance collaborative trust with upstream and downstream enterprises, and make good use of industry association platforms to transform practical experience into standard consensus," Cao Changfeng said.
Scenario 3: Data Centers: Ecosystem Adaptation and Performance Optimization Lead the Way
Facing high-performance scenarios such as data centers, leading RISC-V enterprises continue to make breakthroughs in server-level CPU cores, computing chips, and management control chips. Meanwhile, the adaptation of basic software such as operating systems, virtualization, containers, and AI frameworks must not only be in sync with the R&D of RISC-V chips but also precede the commercialization of the chips.
At the 2026 Xuantie RISC-V Ecosystem Conference held in March this year, Tang Xiong, Vice President of ZTE Corporation, introduced the RISC-V-based AI software stack. This software stack unifies heterogeneous architectures, is compatible with different RISC-V chips and GPU modules, and provides a unified interface to enable seamless use by users. "We have cut average inference latency by 43% and boosted throughput to 2.48x the baseline. Through performance optimization and the adaptation and deployment of AI frameworks, we are gradually making RISC-V AI shift from usable to user-friendly," Tang Xiong said.
During the adaptation of the Xuantie CPU, ZTE and Alibaba DAMO Academy carried out multi-layered collaboration. In terms of computing infrastructure, they completed the adaptation of core Kubernetes and OpenStack components in the RISC-V environment. For ecosystem expansion, they pushed relevant compilation and performance optimization PRs (Pull Requests) to upstream communities and ported middleware, databases, and toolchains to the RISC-V architecture. At the foundational library level, they cumulatively provided over 90 PRs to upstream communities, jointly promoted four international standards, boosted X264 and X265 video encoding and decoding performance to 330% and 285% of the baseline, respectively, increased encryption and decryption algorithm performance by more than three times, and boosted ISA-L library performance by nearly 100 times.
"In the future, we will gradually expand the scope of cooperation, deeply extend into core scenarios such as computing, continuously optimize performance, promote standard unification, and lead the large-scale application of RISC-V in data center scenarios," Tang Xiong said.
How to Enhance Ecosystem Maturity?
Over the past three years, RISC-V has continued to evolve in terms of its standard system, hardware capabilities, and basic software ecosystem, with application scenarios shifting from development board verification to industry deployment. However, ecosystem maturity, especially regarding adaptation and optimization for open commercial software, still needs improvement.
"The current RISC-V ecosystem has moved from the early stage of 'architecture feasibility verification' to a new stage of 'systematic ecosystem construction and scenario-based deployment.' RISC-V is no longer just a choice for a certain type of low-power chip, but is evolving towards a more complete computing ecosystem," Li Zhenning pointed out. "However, compared to mature ecosystems like x86 and Arm, RISC-V still has gaps in the number of commercial software offerings, driver richness, performance tuning, standardized verification, and industry-scale applications."
The reason ecosystem adaptation is most difficult for commercial software is that they have a large user base, frequent application iterations, diverse software sources, and higher requirements for delivery cycles and stability. Manufacturers and developers will adopt a more cautious attitude towards replacing or introducing new architectures.
"The commercial native adaptation of RISC-V cannot rely solely on sentiment or single-point breakthroughs; it must adopt a strategy of 'scenario-driven, layered promotion, ecosystem co-construction, and compatible transition,'" Li Zhenning said, proposing four suggestions in this regard.
First, choose appropriate breakthrough scenarios. RISC-V is more suitable for entering scenarios such as educational development, industrial control, edge AI, robotics, IoT (Internet of Things), and dedicated terminals. These scenarios have stronger demands for openness, customizability, cost, and long-term controllability, and it is easier to form joint hardware and software optimization.
Second, establish a layered adaptation mechanism. At the underlying layer, chip manufacturers and operating system communities solve kernel, driver, firmware, and toolchain issues; at the middle layer, distributions and communities solve software packages, runtime libraries, and development environment issues; at the upper layer, application vendors, industry partners, and users jointly complete business software verification.
Third, adhere to native-first and allow compatible transitions. For core commercial software, the ultimate goal is the native RISC-V version. However, in the early stages of the ecosystem, user migration thresholds can be lowered through compatibility layers, remote applications, and cloud collaboration to buy time for native adaptation.
Fourth, provide certainty for commercial software vendors. This includes stable system versions, clear ABI/API compatibility commitments, continuous testing environments, real hardware resources, adaptation certification mechanisms, and joint promotion opportunities.
"The core of RISC-V's transition from 'usable' to 'user-friendly' is not just about the benchmark score improvement of a single processor or the release of a single system image, but whether the hardware and software ecosystem can continuously iterate around real scenarios. openKylin will continue to play the bridge role of the open-source operating system community, uniting upstream and downstream partners to transform RISC-V's open advantages into implementable, verifiable, and sustainable industrial capabilities," Li Zhenning stated.
Author丨Zhang Xinyi Editor丨Qiu Jiangyong Art Editor丨Malia Supervisor丨Lian Xiaodong