On October 19, the 6th RISC-V China Summit was held at the Shenzhen Convention and Exhibition Center. Leerui Micro, a subsidiary of ZTE Microelectronics, officially unveiled its first high-performance RISC-V CPU chip for intelligent computing centers, the "Everest 200".
According to the materials released at the event, the Everest 200 features the following six major characteristics:
- Advanced RISC-V Architecture: Based on the latest RVA23 profile, it supports Hypervisor, AIA, CoVE, and RVV1.0 (Vector Extension 1.0). Notably, RVA23 is a critical baseline for RISC-V to enter the application processor and server markets. Supporting it ensures basic software ecosystem compatibility. AIA (Advanced Interrupt Architecture) and Hypervisor are crucial for server virtualization and cloud-native scenarios.
- High-Performance, High-Density Computing: Featuring a 64-bit superscalar out-of-order architecture with wide decode width, advanced branch prediction, and highly deterministic real-time execution capabilities. This indicates that the CPU core of the Everest 200 is an out-of-order execution architecture designed for high performance, rather than a simple in-order pipeline.
- Native AI Acceleration: Equipped with high-throughput Vector + Matrix computing, it features hardware acceleration for RAG retrieval and reranking, and is claimed to be capable of running hundred-billion-parameter MoE large models. This aligns with the KV Cache optimization for the "Inference Super Node Host CPU" — the Matrix/Vector units handle AI computing on the CPU side, while the compression/encryption engines manage data movement and security.
- High-Bandwidth, Large-Capacity Memory: Supporting the highest DDR5 standards, DDR MRDIMM, and large memory capacity expansion. MRDIMM is a new-generation high-bandwidth memory module, ideal for bandwidth-sensitive workloads such as AI inference.
- High-Performance Interfaces: Supporting PCIe 6.0 and CXL 3. CXL 3 is a critical interface for current memory expansion and pooling. When GPU VRAM is insufficient in an intelligent computing center, CXL allows CPU-side memory to serve as an "overflow area" for large models, which is particularly valuable for long-context inference.
- High Energy Efficiency: Lower power consumption, higher energy efficiency ratio, and better TCO.
However, ZTE Microelectronics did not disclose the specific parameters of the "Everest 200" at the event. It is expected to be officially released by the end of this year.
According to Shi Yijun, General Manager of the Wireless and Computing Power Business at ZTE Microelectronics, the "Everest 200" will primarily target Agent CPU clusters, inference super node Host CPUs, and enterprise-level intelligent computing hybrid inference in terms of applications.
Agent CPU Clusters: High-density computing cores designed for Agent scenarios, emphasizing RISC-V instruction-level acceleration to improve Agent execution efficiency. Agent workloads are characterized by a massive number of lightweight, concurrent task scheduling and tool invocations, requiring the CPU to maintain low-latency responses under high concurrency.
Inference Super Node Host CPU: Serving as the "host" CPU for GPU/accelerator card clusters, it runs inference for small and medium-sized LLMs and features instruction-level acceleration for KV Cache. KV Cache is the primary source of VRAM/memory consumption in large model inference. Especially in long-context scenarios, optimizing KV Cache management and data movement at the CPU level directly impacts inference economics and the usable length of the context window.
Enterprise-Level Intelligent Computing Hybrid Inference: Supporting an integrated solution of RISC-V native AI + XPU accelerator cards, where the "cold experts" in the MoE of large models are executed by the CPU. In the MoE architecture, not all experts are activated. Running the computation for cold experts on the CPU and hot experts on the GPU/accelerator cards is a practical approach to reducing the TCO of intelligent computing centers.
Editor: Xinzhi Xun / Langke Jian