Author: Jiu Lin
In 2018, a development board priced at USD 999 appeared on the hardware crowdfunding platform Crowd Supply. Named HiFive Unleashed, it was developed by the RISC-V chip company SiFive. The most prominent introduction on the project page was: the world's first RISC-V development board capable of running Linux.
Looking back today, this selling point seems somewhat modest. However, for developers at the time, being able to get their hands on real hardware, run systems on it, and port software already marked a step forward for RISC-V toward practical applications.
Eight years later, RISC-V has moved into more complex computing scenarios.
In March this year, DAMO Academy released the XuanTie C950. This processor set a new RISC-V performance record with a 3.2GHz clock frequency and a single-core SPECint2006 score exceeding 70. As performance improves, the tasks facing the team have become more specific: how to enable more software to make the most of this CPU, and how to ensure its long-term stable operation in complex workloads.
Today, at the 2026 RISC-V China Summit, DAMO Academy showcased new progress of the C950 in multi-core interconnection, AI inference, and server Java, while simultaneously releasing the automotive-grade enhanced processor IP XuanTie E908A and unveiling its product roadmap for autonomous driving and embodied intelligence for the first time. Behind these explorations lies the accumulation of large-scale applications. XuanTie has shipped over 6 billion units in total, covering various scenarios including smart terminals and server peripherals. Starting from these stably shipped products, XuanTie is delving deeper into more complex computing tasks such as server CPUs and autonomous driving.
From a high-performance CPU to practical applications in servers, automobiles, and robots, there is still a massive amount of software adaptation and engineering validation work in between. Meng Jianyi, Chief Scientist of DAMO Academy, stated at the summit: "For high-performance RISC-V to truly achieve mass production and deployment, it requires not only benchmark processor products but also continuous software and hardware technology R&D and engineering validation to refine it from being 'usable' and 'reliable' to achieving outstanding performance."
01. After Getting the Ticket to the High-Performance CPU Arena
From C910 to C950, XuanTie has spent nearly seven years continuously raising the performance ceiling of RISC-V.
In 2019, the SPECint2006 score of the C910 was about 7 points/GHz; in 2025, the C930 pushed this number to 15 points/GHz; and in March this year, the C950 exceeded 22 points/GHz. Whether RISC-V can produce high-performance CPUs has been answered by XuanTie through several generations of products.
Half a year later, the tests facing the C950 have further extended to multi-core collaboration and specific workloads.
Multi-core efficiency is a test that high-performance CPUs must pass when entering the server market. In 2024, when Cloudflare selected processors for its 12th-generation servers, it compared three AMD products: two with 96 cores and one with 128 cores. The ultimate winner was the 96-core EPYC 9684X. In its production environment, this processor delivered 2.45 times the performance of the previous-generation server, while the 128-core product achieved 2.15 times. The one with the most cores did not become the final winner. One of the differences lies in the cache: the winning product was equipped with a larger L3 cache for each core, keeping more data inside the chip and reducing the wait time for accessing external memory.
The C950 faces similar tests. A single core running fast does not mean that putting dozens of such cores together will yield dozens of times the performance. When multiple cores request data simultaneously, they must compete for bandwidth; the data copies saved by each core must also remain consistent. If not handled properly, the added cores will spend their time waiting.
DAMO Academy disclosed that through the multi-core interconnect product XT-LINK, the multi-core performance linearity of the C950 has exceeded 75%. In other words, the performance of multi-core collaborative operation reaches more than three-quarters of the sum of the independent performance of each core. This means that in these tests, most of the computing power brought by adding cores can be truly utilized. For enterprises designing chips with XuanTie IP, this step is crucial: after improving single-core performance, it is also necessary to minimize the loss in multi-core collaboration to create a server processor capable of handling a large number of concurrent tasks. Meanwhile, changes in AI applications have brought new opportunities for the C950. When an agent completes a task, in addition to calling models, it may also need to query databases, run code, invoke tools, and then process the returned results. A significant portion of these tasks relies on the CPU. Users are waiting for the entire task to be completed, and any slowdown in any part will affect the final experience.
This is also the focus of the C950's optimization this time. According to the test results published by DAMO Academy, across four types of Agentic workloads, the C950 has a performance advantage of over 10% compared to the mainstream traditional architecture processors it was benchmarked against; in terms of model inference, running Qwen3.8-Flash-Next reaches 43 tokens/second, and running DeepSeek V4-Flash reaches 38 tokens/second. Supporting these optimizations is the matrix computing capability added to the C950 beyond general-purpose computing. The team accelerates model operations through its proprietary TPE matrix extension, while optimizing the memory architecture, special functions, and software, enabling closer coordination between business processing and inference, which is "general-inference integration." Meng Jianyi revealed to reporters: "For models under 30B, the C950 has a significant advantage in task collaboration for Agentic AI."
Following this approach, XuanTie is also exploring pairing small cores with more powerful AI computing modules to build XPUs for dedicated acceleration scenarios. With RISC-V as the common foundation, different chips can adjust their computing architectures around model requirements while continuing the existing software ecosystem. From setting a benchmark for high-performance CPUs to promoting mass production and deployment, DAMO Academy's approach has always been clear: first make the CPU strong, set a benchmark for high performance, build industry confidence, and then add capabilities around specific applications. The continuous refinement over the past half-year is precisely turning the initial performance achievements into advantages that more applications can utilize.
When discussing what customers really care about, Meng Jianyi compared the benchmark test scores achieved by the C950 in March to getting a "ticket to the 150-kilogram class competition," stating: "After getting the ticket, everyone will next watch to see who we can actually defeat in specific competitions." The C950 has already given XuanTie the capability to participate in this high-performance competition. What needs to be strived for next is for customers to be willing to include RISC-V in their choices when designing their next products.
02. RISC-V Steps into the Era of Physical AI
This time, another important release from DAMO Academy is a product roadmap targeting autonomous driving and embodied intelligence. The automotive-grade enhanced processor IP XuanTie E908A made its debut, and the high-performance automotive-grade processor C950A has also entered the planning phase. From servers to automobiles and robots, XuanTie is pushing the CPU technology accumulated over the past few years into a broader application market.
This move is not sudden; RISC-V's advance into the automotive sector has long been traceable. Infineon has announced the launch of a new series of automotive microcontrollers based on RISC-V, covering a wide range of applications from entry-level to high-performance. Domestically, Great Wall Motor and Zijing Semiconductor, Dongfeng Motor and Binary Semiconductor, JAC Motors and Xinche Wuxian, among others, are also jointly promoting the R&D and industrialization of automotive-grade RISC-V MCUs. Market research institutions have also given positive expectations. According to estimates in an SHD research report, revenue from RISC-V SoCs in the automotive sector will be about USD 1.84 billion in 2025, and is expected to grow to USD 12.3 billion by 2031, with a compound annual growth rate of 37.3%. However, there are many types of chips in a car. The requirements for computing power and safety vary greatly between controlling car lights, managing batteries, and processing autonomous driving tasks.
The roadmap presented by XuanTie this time targets both high-level functional safety and high-performance computing. First is the E908A, primarily aimed at scenarios such as safety islands, domain controllers, and in-vehicle gateways. It is the industry's first RISC-V CPU IP that simultaneously meets ASIL-B and ASIL-D requirements, with a Single-Point Fault Metric (SPFM) exceeding 90%. It should be noted that ASIL-D is the highest level in automotive functional safety ratings.
The safety requirements for automotive chips are often hidden in places invisible to ordinary users. Taking the safety island targeted by the E908A as an example, it is responsible for monitoring system status, executing safety-related tasks, and participating in fault handling when anomalies occur. It may not have the most powerful computing power in the entire chip, but it needs to work reliably when other modules encounter problems. This is also why automotive-grade processors are difficult to develop: they must consider how to complete tasks under normal conditions, and also plan ahead for what to do after a fault occurs. From high-performance records to the highest level of automotive functional safety requirements, XuanTie is establishing another benchmark for RISC-V. The former allows chip companies to see the performance potential of open architectures, while the latter gives them the opportunity to use RISC-V in positions that bear higher safety responsibilities.
Greater ambition in the roadmap lies in the C950A. As the automotive-grade version of the C950, it is primarily aimed at autonomous driving, with a target performance reaching five times that of existing RISC-V automotive-grade products. According to information obtained by Semiconductor Industry Observer, the C950A plans to retain the performance level of the C950 and complete automotive-grade optimization, with an expected launch by the end of 2027.
This means that DAMO Academy hopes to bring the high-performance CPU capabilities already established in the server direction to the core computing links of automobiles. In autonomous driving chips, AI accelerators handle a large amount of model computation, while the CPU must run complex programs, schedule tasks, and coordinate various computing modules. The continuous improvement in model capabilities also poses new requirements for the general-purpose computing that supports its operation.
In the interview, Meng Jianyi also revealed a clear judgment to Semiconductor Industry Observer: between the two directions of automobiles and robots, he is more optimistic about RISC-V taking the lead in breaking through in autonomous driving. What he values is the demand for computing power here; in contrast, multimedia and entertainment applications in the cockpit still have deep software ecosystem barriers. Looking further ahead, autonomous driving and embodied intelligence also pose common requirements for processors. Compared to Agentic AI, Physical AI has higher requirements for computing power and real-time performance, requiring further expansion on the basis of general-purpose computing. The scalability of RISC-V is providing space for these explorations.
03. Beyond a Single Core, There Is a Whole World
Beyond product progress, DAMO Academy also disclosed a set of less conspicuous numbers this time: its RISC-V-related contributions to the GCC community rank second globally, over half of the RISC-V code in the OpenJDK community comes from DAMO Academy, and it has provided 2,796 open-source compatibility test cases to the international foundation's CSC certification baseline. They are not as eye-catching as clock frequencies and benchmark scores, but they determine whether RISC-V can move from technological breakthroughs by a few companies to the prosperity of the entire industry. The release of a processor is still far from customers truly using it; there is much work to be done. Operating systems need support, compilers need optimization, and applications need adaptation; after the programs run, they still need to be tested, fixed, and maintained. Meng Jianyi repeatedly emphasized that moving from usability to mass production are two completely different stages. High-performance products set the benchmark, and the work carried out around them is what allows an architecture to take root. Since entering the RISC-V field, DAMO Academy has advanced processor R&D and ecosystem building together. These investments have continuously deepened involvement in international open-source projects such as GCC, LLVM, and OpenJDK, and are gradually reflected in the performance of practical applications.
According to the data disclosed this time, DAMO Academy's relevant optimizations in GCC have brought a typical performance improvement of over 10% to RISC-V processors; the deep adaptation and optimization of server Java for XuanTie C950 have achieved a 30% performance improvement. XuanTie processors have also gained support from multiple commercial operating systems, running large-scale commercial software such as Taobao, DingTalk, WeChat, and WPS on top of them.
These years of continuous investment have made DAMO Academy an important open-source contributor and standard setter in the international RISC-V community. The XuanTie team serves as chair or vice-chair in 2 technical committees and over 10 technical task groups of RISC-V International. Li Chunqiang, a senior technical expert at DAMO Academy, summarized its ecosystem model as "led by leaders, open and inclusive": accumulating experience through product R&D, and then promoting the co-evolution of technology through community cooperation. Especially as more and more manufacturers join, how to keep different RISC-V products compatible has become a problem the entire industry must face. DAMO Academy's participation in the construction of the RVI CSC certification baseline, and the 2,796 open-source test cases mentioned earlier, are precisely aimed at turning the requirements in the specifications into executable checks, providing a common foundation for open innovation.
Facing new computing demands, DAMO Academy, together with the Beijing Open Source Chip Research Institute and ZTE Microelectronics, is exploring spatial multithreading technology, achieving phased results with a 30% dual-thread performance gain. It is expected that by 2028, the total SPECint2006 performance of RISC-V single-core multithreading is expected to exceed 100 points. Meanwhile, DAMO Academy participates in the construction of the Ruyi community by the Institute of Software, Chinese Academy of Sciences, and jointly promotes software adaptation and AME matrix computing instruction set extensions with more than 20 domestic and foreign institutions, enabling new computing capabilities and software support to develop together.
At the global software ecosystem level, the DAMO Academy XuanTie team is also a founding member of the global RISC-V software ecosystem initiative RISE. By contributing ecosystem development boards and promoting software adaptation and optimization, they work with international peers to improve the RISC-V software ecosystem. For China's RISC-V industry, the weight of this work lies in the fact that Chinese teams are bringing their technological accumulation into the joint construction of global computing architectures and software ecosystems.
04. Conclusion
The history of computing architectures is often measured in decades. Today, AI is opening up new innovation space for RISC-V. From agents processing complex workloads to automobiles and robots perceiving and acting, new applications are constantly changing the tasks that chips need to undertake, also providing a broader field for openness and scalability.
DAMO Academy's practice is a microcosm of this industrial exploration. Making the processor strong, refining the product to be reliable, and then bringing technical experience into the open-source community and international standards, corporate innovation becomes the driving force for the entire architecture to move forward. Meng Jianyi said: "We believe that RISC-V will ultimately succeed, which is related to its characteristics: originating from scientific research innovation, succeeding in industrial practice, and thriving in open cooperation."
The future of RISC-V will be co-created by global participants. And China's chip industry is participating in and driving it forward with increasingly solid technological contributions.