I. Paradigm Shift in the First Year of Physical AI: From Digital Twin to Embodied Interaction
The World Artificial Intelligence Conference 2026 (WAIC 2026) reveals that the AI industry has officially transitioned from the predictive simulation of the "Digital Twin" era to the real-time closed-loop intervention of the "First Year of Physical AI." The evolutionary logic of Embodied AI has undergone a fundamental shift: moving from executing single preset actions to closed-loop "autonomous operations" in real-world working scenarios such as depalletizing, assembly, and emergency disaster relief. This paradigm shift requires the system to possess extremely high-dimensional perception-decision-execution continuity, essentially evolving from "probabilistic prediction" in the digital world to "real-time deterministic intervention" in the physical world.
The breadth and depth of Vision-Language-Action (VLA) model deployment on the edge have become the cornerstone for measuring the intelligence level of robots. However, the extreme pursuit of Token throughput by VLA models and the current limitations of edge resources have made the localization of large model inference a technical imperative:
· Absolute Physical Safety: Localized operation eliminates the random fluctuations of cloud connections, ensuring that robots exhibit millisecond-level deterministic behavior under extreme working conditions. · Low-Latency Closed-Loop Control: Physical operations require extremely high real-time response speeds, and local inference can avoid the decision-making lag caused by cloud data transmission. · System Bus Cost and Privacy: Edge inference avoids the bandwidth costs caused by the massive backhaul of multimodal sensor data and ensures data privacy at industrial sites from the hardware level.
Embodied AI poses a severe "triangular barrier" for edge and endpoint chips: the game among computing latency, power consumption, and on-chip bandwidth. Traditional memory architectures waste up to 70%-80% of energy when handling the massive transfer of parameters, and can no longer support the high-frequency iteration of VLA models. Therefore, architectural innovation in underlying chips—especially the disruption from data flow reconstruction to memory systems—has become the key to breaking through the trillion-level agent market.
II. Path Selection for Edge Processor Cores: Arm Heterogeneous Computing vs. RISC-V Open-Source Ecosystem
In embodied AI hardware, the CPU core undertakes the core function of "brain" scheduling, responsible for processing complex RTOS (Real-Time Operating System) tasks, multimodal data stream synchronization, and the operation of robot operating middleware (ROS 2).
· Arm Architecture: Establishing Commercial Dominance with Automotive-Grade Accumulation
Relying on a mature ecosystem and high integration of multi-core heterogeneity, the Arm architecture remains the mainstream choice for mass-produced products. Manufacturers precisely match the different computing power requirements of the "primary and secondary brains" for embodied AI robots through asymmetric multi-core designs.
Architecture Metric Evaluation of Representative Arm Architecture Edge AI Chips Displayed at WAIC
· RISC-V Architecture: Reconstructing Flexibility and Resolving System Fragmentation
The rise logic of RISC-V has transcended the mere "royalty-free" category. Its core value lies in the customizable flexibility of the instruction set, which provides a strategic path to resolve the fragmentation of embodied AI systems. By integrating customized RTOS scheduling instructions into RISC-V cores, vendors such as Yixing Intelligence, SpacemiT, and Nanocorechip are committed to unifying the "brain-body" interface standards. Furthermore, Nanocorechip is attempting to build an ecological moat for domestic computing power at the underlying operator library level by establishing the world's first RISC-V Compute-in-Memory (CIM) standard.
Architecture Comparison: Arm provides extremely high engineering maturity and automotive-grade safety, while RISC-V solves the pain points of endpoint system fragmentation through customized instructions. The evolution of both at the scheduling core level is forcing the acceleration of memory architecture towards breaking through the "memory wall."
III. Conquering the "Memory Wall" and "Energy Wall": System-Level Disruption of Memory Architecture
The high-frequency Token output of VLA large models poses nearly cruel requirements for memory access bandwidth. When running Transformer algorithms, the traditional von Neumann architecture generates massive energy loss due to the millimeter-level data transfer process between logic units and memory units.
· 3D Stacking and Near-Memory Computing: Sub-Micron Physical Leap
The DF1000 launched by Dongfang Suanxin is the architectural benchmark in this field. Through wafer-level 3D hybrid bonding of DRAM-Logic, this chip achieves vertical compression of the computing layer and the memory layer. The key technological breakthrough lies in the reduction of its interconnect pitch to the sub-micron level (Sub-micron pitch), which drastically reduces the data transmission distance from the millimeter level to the micron level. This extreme physical compression unleashes a memory access bandwidth of 6.4 TB/s. This enables the DF1000 to utilize the mature 14nm process node and, through dynamic reconstruction of hardware resources, benchmark the performance metrics of advanced 4nm process chips, achieving a true "overtaking on a new track."
· SRAM Compute-in-Memory (CIM) and Vector Systolic Arrays
Compute-in-Memory technology thoroughly resolves the energy efficiency bottleneck by eliminating the data transfer process.
· HoumoAI M50: Based on the SRAM-CIM architecture, it achieves 160 TOPS of physical computing power with an ultra-low power consumption of only 10W. Its strategic value lies in realizing the edge offline deployment of models with 30B to 120B parameters, greatly alleviating the real-time performance degradation caused by the memory wall. · MetaChip LPU: This architecture adopts a Vector Systolic Array (VSA/G-VSA), which increases the main memory bandwidth utilization to 92% through precise data flow control. Combined with Dynamic Mixed Precision Control (SCV) technology (supporting dynamic switching from 1-bit to 8-bit), MetaChip achieves a Token output rate of 80 tps for 7B models at a power consumption of 5W.
The system-level transformation of memory architecture marks that the operation of large models in the ultra-low power consumption range of 5W-10W has now achieved industrial practical value.
IV. Reconfigurable Parallel Processors: Reshaping the Ecosystem Between Flexibility and Energy Efficiency
Facing the rapidly changing embodied AI algorithms (such as the rapid migration from CNNs to Transformers and Diffusion models), the flexibility defects of ASICs are becoming increasingly prominent. Reconfigurable computing technology (CGRA/RPP) provides near-ASIC energy efficiency and near-GPU flexibility through hardware-reconfigurable data paths.
· Tsingmicro's CGRA Architecture: It achieves a system response of less than 30ms under a false recognition rate of one in ten million. More importantly, this architecture possesses system-level dynamic self-healing reconfiguration capabilities. Under extreme space conditions such as radiation resistance, it can ensure the continuity of logic computing through self-repair at the architecture level. · Xindongli's RPP Architecture: It adopts a differentiated path of "comprehensive CUDA compatibility," significantly reducing the code reconstruction cost of migrating from the Nvidia ecosystem to domestic edge endpoints. In terms of physical design, it adopts substrate-less FC-BGA packaging (Substrate-less Fan-out), which significantly optimizes the volume of edge inference terminals while improving the integrity of high-density signal interconnection.
This hardware-software decoupling and extensive ecosystem compatibility strategy provides engineering guarantees for embodied AI chips to leap from laboratory prototypes to the stage of large-scale mass production and delivery.
V. Domestic Edge AI Chip Adaptation Matrix and Industrial Implementation Evidence
Relying on the overwhelming technological advantage and ultimate cost-effectiveness of vehicle intelligent driving, domestic edge AI chips are building a full-scenario adaptation matrix in the robot market.
Domestic Embodied AI Chip Scenario Adaptation Matrix
· Analysis of Competitive Advantages of Industrial Camps
1. "Full-Brain System" Transplant Camp (Horizon Robotics, Black Sesame Technologies): Relying on profound automotive-grade safety accumulation, it smoothly transplants mature visual algorithms and world models from vehicle intelligent driving to high-level cognitive scenarios of humanoid robots. 2. High Cost-Effectiveness Control Base Camp (Rockchip): Relying on a mature SoC engineering system, it provides highly competitive thousand-yuan-level mature solutions in scenarios such as dexterous hands that require multi-dimensional alignment of vision and touch and high-frequency force control. 3. High-Concurrency Edge Inference Camp (Axera): Utilizing M.2 accelerator cards with power consumption of less than 8W, it achieves a "seamless upgrade" of existing robot central control systems, focusing on high-density offline knowledge base retrieval.
The prosperity of the application layer not only verifies the engineering capabilities of the underlying hardware but also provides massive physical feedback for the subsequent unification of compute-memory standards and the construction of open-source software stacks.
VI. Summary of Industry Trends: Building a New Map of Autonomous and Controllable Computing Power
Synthesizing the technological evolution trends of WAIC 2026, domestic edge AI chips are presenting three inevitable evolution trends:
1. System-Level Innovation Redefines Performance Limits: The "organizational innovation" centered on 3D hybrid bonding stacking and compute-in-memory has proven that on mature process nodes such as 14nm/22nm, advanced process-level performance bursts can also be achieved through sub-micron physical interconnections, effectively circumventing external process blockades.
2. Edge Offline Operation of Large Models Becomes the Cornerstone of Safety: Addressing the extreme operational needs of embodied robots in the physical world, offline inference under ultra-low power consumption of 5W-10W has become an imperative to ensure system stability and data security.
3. Establishment of Open-Source Ecosystem Stacks and Standardized Standards: By being compatible with CUDA and establishing RISC-V compute-in-memory standards, domestic chips are shaking off the shadow of ecosystem fragmentation and entering a new stage of full-stack ecosystem competition.
Domestic chip manufacturers are reshaping the cost structure of the physical AI industry through the reconstruction of underlying architectures (data flow, compute-in-memory) and the innovation of physical packaging (3D stacking, FC-BGA). Domestic computing power platforms have evolved from mere computing power supply to the strategic base empowering agents in the physical world to achieve "autonomous operations."
The comprehensive implementation of domestic computing power platforms in the physical world marks that the intelligent industry has completed the milestone leap from algorithm definition to architecture drive.
Appendix I: Comparison of Technical Indicators of Domestic Edge AI Chips and Platforms in Core Dimensions of Embodied AI
To provide the industry with a systematic and intuitive comparison benchmark, we have horizontally extracted the core technical indicators of 14 mainstream domestic chip manufacturers participating in this year's WAIC exhibition from the perspective of chips and system platforms:
Appendix II: Scenario Positioning and Adaptation Matrix of Domestic Edge AI Chips in Subdivided Fields of Embodied AI
To clearly demonstrate the applicability and competitive positioning of different domestic chips in real physical scenarios, the following table makes a systematic evaluation from dimensions such as robot type, scenario adaptability, and specific practical applications: