Developing a top-tier large AI chip typically takes an industry-standard development cycle of one and a half to two years. But OpenAI has defied convention.
From writing the first line of hardware code in February 2025 (initiating RTL design) to sending the blueprints to TSMC (Taiwan Semiconductor Manufacturing Company) for manufacturing (tape-out) in November, it took only nine months. In late August 2026, OpenAI unveiled the details of this inference chip, named Jalapeño, at Hot Chips, the premier summit in the chip industry.
Can OpenAI, a software company that started with large model algorithms, really overturn the speed of hardware R&D in an instant? The official press release actually hides the truth about the division of labor: OpenAI is responsible for the computing architecture, while Broadcom handles the physical realization of the chip (silicon implementation) and network connectivity.
Peeling back the wrapper of this nine-month miracle, there is actually only one core question:
How much of this chip was hard-earned through OpenAI's in-house R&D, and how much was simply borrowed directly from Broadcom's off-the-shelf inventory? If Broadcom were replaced, how many steps in this lightning-fast in-house development would have to start from scratch?
Figure 1: Development and Deployment Timeline of Jalapeño
I. The Four Types of Work in In-House Chip Development and Who Does What
To see clearly how much of Jalapeño was developed in-house, we cannot just look at who is credited; we need to break down chip manufacturing into four building blocks:
1. Function and Architecture (Computing Brain): Personally handled by OpenAI
Function and architecture refer to workload definition, architecture, RTL, and the software stack. This is the soul of the chip, determining how fast it runs large models and what tasks it specializes in. This part was almost entirely led and developed in-house by OpenAI. According to industry reports, the vast majority of its hardware circuit code (RTL) was rewritten from scratch.
More critical details come from leaks by SemiAnalysis. On the hardware side, this chip cut out all redundancies unrelated to large model inference, with extremely aggressive trade-offs; but the harder hurdle actually lies in software. Building hardware is easy, but building an ecosystem is hard. Without NVIDIA's mature CUDA toolchain, OpenAI had to build its own compiler and underlying drivers from scratch.
To this end, OpenAI directly utilized its own AI models to automatically write underlying computing kernels day and night. On the timeline, it took nine months to complete the process from the first version of RTL to the final tape-out. After tape-out, it took about three months to build a complete underlying software stack from scratch, and successfully ran the industry's most challenging and compute-intensive heavy inference model, DeepSeek R1, in a very short time.
2. Reusable Modules (Peripheral Communication Pipelines): Directly provided by Broadcom
Reusable modules refer to interface IP, I/O chiplets, and packaging platforms. No matter how powerful the computing core is, it must rely on highways to connect to external memory and networks.
Jalapeño specifically uses a dedicated I/O chiplet responsible for off-chip communication, integrating industry-leading SerDes (high-speed interconnect channels) and HBM (High Bandwidth Memory) interfaces.
For these mixed-signal modules, which are extremely difficult to verify from scratch and highly sensitive to physical processes, OpenAI did not reinvent the wheel, but directly adopted Broadcom's mature silicon-verified assets from its shelf.
3. Project Implementation (From Blueprints to Billions of Transistors): Joint efforts by both parties
Project implementation refers to physical design, packaging co-design, verification, and sign-off.
Turning written code into real transistor layouts and ensuring that billions of circuits do not collide or delay at the nanometer scale (i.e., physical design and verification) is the most time-consuming step in the entire project. This is a combination of Broadcom's experience and OpenAI's algorithms. Broadcom provides a seasoned physical design flow, while OpenAI runs hundreds or thousands of AI agents in batches at night to aggressively accelerate timing convergence and area optimization.
4. Supply and Delivery (Production, Packaging, and Assembly): Managed by Broadcom, with OpenAI helping to secure capacity
Supply and delivery refer to wafers, HBM, packaging and testing, system integration, and mass production management.
According to Tom's Hardware, Broadcom contracted TSMC to manufacture the wafers, coordinated packaging multiple dies into a single package, and collaborated with system vendors to design the entire rack. However, for core resources, OpenAI also had to step in personally, leveraging its customer appeal to lock in the extremely scarce HBM memory capacity.
Obviously, engaging Broadcom is not simple contract manufacturing, nor is it just putting a shell on an existing public mold. What Broadcom sells is a "mature IP component library + seasoned construction flow."
This leads to the most critical dividing line: on Broadcom's side, what exactly was directly assembled using existing in-house assets, and what had to be custom-tailored for OpenAI?
Figure 2: R&D and Delivery Division of Labor for Jalapeño
II. What is Reused: IP, Design Flows, and Packaging Experience
Broadcom's ability to deliver the project within nine months mainly relies on three ready-made assets in its warehouse:
The first is silicon-verified interface IP.
In advanced processes, the physical interfaces responsible for data throughput (such as SerDes and HBM PHY) are the most prone to failure. These mixed-signal modules are extremely sensitive to voltage and manufacturing processes, and are recognized in chip engineering as the most time-consuming and difficult "long poles" to tackle. If in-house R&D starts from scratch, a tape-out failure and subsequent re-spin would wipe out more than half a year. Broadcom holds mature interface solutions already verified on TSMC's production lines. OpenAI directly adopted them for immediate use, which not only saved months of debugging time but also directly avoided the huge risk of starting over.
The second is the packaging platform.
Jalapeño did not cram all functions into a single large blueprint, but adopted a chiplet stitching solution.
Broadcom had already built a ready-made architectural foundation, using a dedicated I/O chiplet for external communication, combined with advanced packaging technology, to stitch the computing core and high bandwidth memory together like building blocks.
OpenAI adopted this established assembly framework, only needing slight adaptations based on its own computing core layout, thereby avoiding the massive engineering effort of redesigning the packaging foundation.
The third is the design flow and the team that has worked on similar projects.
Cramming tens of billions of transistors into a microscopic physical space while ensuring signals do not delay or collide relies on pure engineering muscle memory.
Broadcom has accumulated a full decade of physical design and sign-off experience on the Google TPU project. This highly refined automated flow and the veteran engineers who have navigated countless pitfalls are the invisible pillars that enable Broadcom's IP to be seamlessly and on-time embedded into new projects.
This "building block" approach is even becoming an industry-wide tacit understanding. Even NVIDIA has started packaging and selling its NVLink interconnect platform to solution providers like MediaTek as a foundation—chip manufacturing in the industry has long bid farewell to the method of building from the foundation brick by brick.
So, how much credit does the mythologized "AI acceleration" actually deserve?
In official promotions, OpenAI places "AI agent-accelerated design" on par with Broadcom's capabilities. However, checking publicly available data from various parties, the only confirmed achievement is a 10% reduction in the chip area of the matrix unit through parallel optimization using its own models.
In chip engineering, area reduction, computing power improvement, and schedule shortening are three different things. AI indeed helped engineers share the physical labor of repeatedly running simulations at night, but what truly supported the nine-month tape-out miracle is still Broadcom's invaluable industrial shelf.
III. Two Types of Cooperation Arrangements: What Customers Get in Return
Once mature modules and flows are in place, the next divergence lies in the cooperation model. Who provides the key interfaces, who does the underlying physical implementation, who spends real money to secure scarce HBM memory, and who bears the risk of supply chain mass production? These four watershed issues divide the industry into two distinctly different routes.
The turnkey model, represented by Broadcom and Marvell.
From wafer procurement, physical implementation, advanced packaging to the final full-rack deployment, everything is handled by the service provider. The service provider bears the high risks of component procurement and supply chain yield, and ultimately delivers the finished product directly to the customer.
For frontier labs like OpenAI and Anthropic, which urgently need computing power to support model iteration but lack deep hardware supply chain accumulation, throwing all complex engineering to Broadcom is the shortest path to buying "time and delivery certainty."
The other is the "self-managed" route taken by tech giants as they mature.
Taking Google and Amazon as examples, as their in-house chip teams have grown strong, they have begun to aggressively compress the space for intermediaries—Google directly purchases expensive HBM from major memory manufacturers, keeps the computing core firmly in its own hands, and only hands over the peripheral I/O chiplets to MediaTek; Amazon's in-house chips have iterated from the first to the third generation, with more and more supply chain links directly controlled by itself, leaving only pure physical routing and packaging co-design to design companies like Alchip. Even the same large company will mix these two approaches in different computing matrices to spread the bets.
There is no free shortcut in the world. Customers who choose the turnkey model exchange for ultimate development speed, but pay with high premiums and deep path dependence.
In the chip industry, turnkey design service providers typically add a direct service premium of 10% to 20% on top of the rigid costs of production and shipping.
More fatal than the price increase is the invisible chokehold. Once a customer tries to replace Broadcom in the future, they will face the devastating cost of starting over: Broadcom's tested high-speed interfaces and chiplets are proprietary assets, and the termination of cooperation means the termination of licenses; as long as the interface IP or physical chiplets are changed, the interconnect verification of the entire chip must be redone; and once adjustments to the foundry's advanced packaging solutions are touched, the entire system almost has to revert to the lowest-level reusable modules for redesign.
The so-called "in-house R&D," under the turnkey model, is essentially a high-speed gamble that entrusts its soul to the financial backing of an external giant.
Figure 3: Design and Supply Responsibilities Under Two Cooperation Arrangements
IV. Domestic Market: Internal Accumulation and External Reuse
While OpenAI across the ocean can take it for granted to package and entrust the entire physical foundation to Broadcom, domestic AI chip players face completely different realistic constraints.
Reviewing the periodic reports, prospectuses, and audit inquiry replies of representative companies such as Cambricon, Hygon, Moore Threads, MetaX, Enflame, and Biren, one will find that the so-called "in-house R&D" is essentially a dynamic balance between independent R&D and external procurement.
On the line of internal accumulation, the typical form of most domestic chip companies is to keep the most core computing brain and full-chip-level physical implementation firmly in their own hands, but high-speed interfaces still struggle to break free from external dependence, and the backend manpower that concentrates before tape-out also needs to be borrowed from outside from time to time.
MetaX's disclosure is highly representative—GPU architecture, core computing IP, all the way to full-chip layout, clock tree synthesis, and physical verification, are all developed in-house, but key EDA tools and some high-speed interface IPs still need to be procured from overseas suppliers; and for module-level layout and routing, which is not highly technically difficult but concentrates before tape-out and is the most manpower-intensive, the prospectus frankly states that a part was outsourced to external design companies—in 2024, with intensive investment in the Xiyun C600, the outsourced development fee for the year was nearly CNY 95 million, accounting for about 10% of R&D expenses, of which about half was backend design.
Cambricon, on the other hand, demonstrates the generational reuse of engineering experience internally. Its mastered 7nm advanced process physical design capabilities directly spanned and supported multiple chips from Siyuan 100 to 370; Hygon's problem-solving approach on DCUs, physically splitting computing chiplets and interconnect interface chiplets and then applying advanced packaging, is exactly the same as international giants—and its prospectus and inquiry replies during its 2022 IPO also frankly admitted that backend module-level layout and routing relied on external engineers to supplement manpower.
More pragmatic companies have even made the R&D boundaries into an elastic valve. Biren clarified this commercial reality in its prospectus: the company has a full set of design capabilities, but when facing delivery pressure, it can also choose to outsource some backend and physical design to external design service providers; and once its own team matures or for cost considerations, the previously procured external IPs will be gradually replaced by in-house versions. Moore Threads, after entering the Entity List in 2023, increased the in-house R&D of some IPs, following exactly this path. Enflame's inquiry reply recorded the opening and closing of this valve more specifically: in 2023, module-level physical implementation was handed over to external teams; in 2024, it was switched to domestic manufacturers; in 2025, the new generation of chips is still in the early stages of R&D, and backend outsourcing is temporarily reduced to zero.
Having backend capabilities does not mean doing everything in-house for every project, nor does procuring external support mean completely falling into "assorted OEM branding." In the face of the high investment in advanced processes, many domestic teams are actually moving towards "light design": they control the life-or-death links such as full-chip layout, clock tree, and sign-off themselves, while pushing the most manpower-intensive and fluctuating module-level routing and some packaging design to external professional teams. The inquiry replies from MetaX and Enflame are almost word for word—"The core links of backend design are independently handled by the company, and the outsourced part is the module-level physical design implementation work conducted under the top-level framework set by the company." Hygon's statement during its IPO meant the same thing.
Figure 4: Disclosure of Physical Implementation, IP, and Backend Design Outsourcing by Six Companies
On the line of external reuse, the puzzle of the domestic version of "design arms dealers" is still incomplete.
As the largest domestic chip design service leader, VeriSilicon can already provide mature PCIe 5.0, 112G SerDes, and UCIe interconnect interfaces on high-performance computing platforms, and has undertaken a large number of advanced process custom projects.
But if the benchmarking scale is pulled in front of Broadcom, the shortcomings are equally obvious—in terms of the HBM interface IP necessary to support top-tier large model inference, the domestic public shelf is still blank. More importantly, even using an off-the-shelf platform, VeriSilicon's officially disclosed design cycle usually still takes 9 to 12 months, and complete production delivery takes another 6 to 18 months. Objective physical laws cannot be skipped; no matter who it is, not a single day can be saved in the hard work of turning logic code into physical chips.
As for the full in-house R&D by internet giants like Alibaba's Zhenwu and Baidu's Kunlunxin, apart from the upper-level architecture and computing power deployment being perceivable by the outside world, the source of their underlying interface IPs, the real physical design dominance, and the division of labor in foundry packaging remain hidden beneath the surface of financial reports.
If Broadcom has paved a standard highway directly to tape-out for OpenAI, then the reality for domestic chip manufacturers is to build their own single-log bridge bit by bit, supported by limited external mature modules, relying on their own long-term physical design accumulation and team engineering hand-to-hand combat.
Conclusion
More harsh than how much was developed in-house is what can still be reused in the next generation.
To evaluate any in-house AI chip, there are always two axes: one looks at what it independently pioneered at the cutting edge, and the other looks at what it maximized in reuse at the foundation.
The true value of Jalapeño lies in OpenAI personally tackling the architectural trade-offs defining the computing brain, the rewritten core circuits, and the software stack built from scratch; and the premise for its thrilling nine-month completion is that Broadcom unreservedly laid the foundation at the bottom with silicon-verified interfaces, a mature packaging platform, and a physical implementation flow honed over ten years.
The survival slices of various domestic manufacturers are the same, simply choosing a narrow path of trade-offs between the generational reuse of their own engineering assets and external supply chain procurement.
Tearing off the halo of promotion, what truly determines how far a company can go has never been the speed of winning the first battle, but whether this reuse system can traverse cycles. When entering the second and third generations of chip iteration, how much of the previously accumulated IP, automated flows, and team experience can be transferred intact? If Broadcom's commercial price is too high, does OpenAI have the confidence to replace it without starting over? Facing changes in the external environment, when domestic enterprises are forced to change manufacturing processes and interface standards, how many design blueprints will be ruthlessly scrapped?
Compared to questioning what proportion of this chip is truly in-house, exploring which capabilities are continuously accumulating and which dependencies are constantly strengthening truly touches the most ruthless underlying laws of the chip industry.
(Appendix at the end of the text: Overview of the latest financial and R&D investment of six representative companies)
Disclaimer: This article is industrial research content and does not constitute investment advice. The cited data are all taken from the public compilation of companies' periodic reports, prospectuses, exchange documents, manufacturers' press releases and conference calls, industry conference speeches, and signed research institution reports, and the calibers have been marked accordingly; the "disclosure status" of the six Chinese companies is classified according to their disclosure texts and does not constitute a ranking of capabilities or competitiveness; the estimates from brokerages and experts have been signed and do not represent the judgment of this article. The cycle and cost figures in the text have different calibers and cannot be subtracted or divided from each other; "nine months" refers only to RTL to tape-out, excluding wafer return, debugging, and deployment.
Quantitative Model Introduction:
1 Broadcom Inc.｜OpenAI and Broadcom Unveil LLM-Optimized Intelligence Processor (2026-06-24) https://investors.broadcom.com/news-releases/news-release-details/openai-and-broadcom-unveil-llm-optimized-intelligence-processor
2 Broadcom Inc.｜Broadcom Inc. Announces Third Quarter Fiscal Year 2026 Financial Results (2026-09-02, including conference call) https://investors.broadcom.com/news-releases/news-release-details/broadcom-inc-announces-third-quarter-fiscal-year-2026-financial
3 Broadcom Inc.｜Broadcom Delivers Industry's First 3.5D F2F Technology for AI XPUs https://investors.broadcom.com/news-releases/news-release-details/broadcom-delivers-industrys-first-35d-f2f-technology-ai-xpus
4 NVIDIA｜NVIDIA and MediaTek Deepen Long-Standing Partnership to Build AI Edge to Cloud Computing Platforms (2026-08-31) https://nvidianews.nvidia.com/news/nvidia-and-mediatek-deepen-long-standing-partnership-to-build-ai-edge-to-cloud-computing-platforms
5 Marvell Technology, Inc.｜Form 8-K (2026-08-19) https://www.sec.gov/Archives/edgar/data/1835632/000119312526356217/d412696d8k.htm
6 ServeTheHome｜OpenAI Jalapeno Custom AI ASIC at Hot Chips 2026 https://www.servethehome.com/openai-jalapeno-asic-at-hot-chips-2026/
7 ServeTheHome｜Google's TPUv8s for Training and Inference at Hot Chips 2026 https://www.servethehome.com/googles-tpuv8s-for-training-and-inference-at-hot-chips-2026/
8 Tom's Hardware｜Hot Chips 2026: OpenAI's Jalapeño AI ASIC unpacked https://www.tomshardware.com/tech-industry/artificial-intelligence/hot-chips-2026-openais-jalapeno-ai-asic-unpacked-accelerator-developed-using-ai-achieves-efficiency-and-throughput-gains-against-power-hungry-blackwell
9 SemiAnalysis｜OpenAI Jalapeño: Better Than Nvidia Blackwell (2026-08-25) https://newsletter.semianalysis.com/p/openai-jalapeno-better-than-nvidia
10 Counterpoint Research｜MediaTek to Contribute 1 in 4 AI ASIC Server Compute Shipments in 2028 (2026-04-29) https://counterpointresearch.com/en/insights/MediaTek-to-Contribute-1-in-4-AI-ASIC-Server-Compute-Shipments-in-2028
11 Futurum Group｜Jalapeño in Nine Months: Did AI Just Break Chip Design Timelines? https://futurumgroup.com/insights/jalapeo-in-nine-months-did-ai-just-break-chip-design-timelines/
12 Brokerage Research Reports and Expert Interviews (Retrieved via AlphaSense Platform)｜UBS (2024-02-27; 2026-08-31), Bank of America Securities (2024-04-19; 2026-08-31), RBC (2026-09-03); Expert Interview Minutes (2026-02-18; 2026-03-02) https://research.alpha-sense.com/
13 Cambricon Technologies Co., Ltd. (688256.SH)｜2026 Semi-Annual Report http://file.finance.sina.com.cn/211.154.219.97:9494/MRGG/CNSESH_STOCK/2026/2026-8/2026-08-08/12484346.PDF
14 Hygon Information Technology Co., Ltd. (688041.SH)｜2026 Semi-Annual Report http://file.finance.sina.com.cn/211.154.219.97:9494/MRGG/CNSESH_STOCK/2026/2026-8/2026-08-14/12492765.PDF
15 Moore Threads Intelligent Technology (Beijing) Co., Ltd. (688795.SH)｜Prospectus for Initial Public Offering and Listing on the SSE STAR Market (Draft, 2025-06-30) https://static.sse.com.cn/stock/disclosure/announcement/c/202506/002098_20250630_D74O.pdf
16 Moore Threads Intelligent Technology (Beijing) Co., Ltd. (688795.SH)｜2026 Semi-Annual Report http://file.finance.sina.com.cn/211.154.219.97:9494/MRGG/CNSESH_STOCK/2026/2026-8/2026-08-10/12484622.PDF
17 MetaX Integrated Circuits (Shanghai) Co., Ltd. (688802.SH)｜Announcement of Listing on the SSE STAR Market for Initial Public Offering (2025-12-16) https://file.finance.qq.com/finance/hs/pdf/2025/12/16/1224879165.PDF
18 MetaX Integrated Circuits (Shanghai) Co., Ltd. (688802.SH)｜2026 Semi-Annual Report http://file.finance.sina.com.cn/211.154.219.97:9494/MRGG/CNSESH_STOCK/2026/2026-8/2026-08-31/12574572.PDF
19 Shanghai Enflame Technology Co., Ltd. (688801.SH)｜Prospectus for Initial Public Offering and Listing on the SSE STAR Market (Disclosed on 2026-09-08) http://file.finance.sina.com.cn/211.154.219.97:9494/MRGG/CNSESH_STOCK/2026/2026-9/2026-09-08/12588272.PDF
20 Shanghai Biren Technology Co., Ltd. (6082.HK)｜Prospectus (2025-12-22) https://www1.hkexnews.hk/listedco/listconews/sehk/2025/1222/2025122200020_c.pdf
21 Shanghai Biren Technology Co., Ltd. (6082.HK)｜Interim Results Announcement for the Six Months Ended June 30, 2026 (2026-08-28) https://www1.hkexnews.hk/listedco/listconews/sehk/2026/0828/2026082800454_c.pdf
22 VeriSilicon Microelectronics (Shanghai) Co., Ltd. (688521.SH)｜2026 Semi-Annual Report http://file.finance.sina.com.cn/211.154.219.97:9494/MRGG/CNSESH_STOCK/2026/2026-8/2026-08-18/12500330.PDF
23 Brite Semiconductor (Shanghai) Co., Ltd. (688691.SH)｜2026 Semi-Annual Report http://file.finance.sina.com.cn/211.154.219.97:9494/MRGG/CNSESH_STOCK/2026/2026-8/2026-08-28/12559219.PDF
24 Montage Technology Co., Ltd. (688008.SH)｜2026 Semi-Annual Report http://file.finance.sina.com.cn/211.154.219.97:9494/MRGG/CNSESH_STOCK/2026/2026-8/2026-08-29/12570414.PDF
25 Alibaba Group｜June Quarter 2026 Results (Form 6-K, 2026-08-20) https://www.sec.gov/Archives/edgar/data/1577552/000110465926099220/tm2623667d1_ex99-1.htm
26 Alibaba Group｜Earnings Call Transcript on August 20, 2026 (Compiled by Investing.com) https://www.investing.com/news/transcripts/earnings-call-transcript-alibaba-q1-2026-sales-rise-9-as-ai-spend-weighs-on-profit-93CH-4870067
27 Shanghai Stock Exchange｜SSE STAR Market Issuance and Listing Audit Information Disclosure: Prospectuses and First Round of Audit Inquiry Replies of MetaX, Enflame, Moore Threads, and Hygon (Cited in Figure 4 and Chapter IV)
MetaX｜Prospectus (Registered Draft, 2025-10-24) https://static.sse.com.cn/disclosure/announcement/c/202510/002078_20251024_OAW7.pdf
MetaX｜First Round of Audit Inquiry Reply (2025-08-27) https://static.sse.com.cn/disclosure/announcement/c/202508/002078_20250827_OO1E.pdf
Enflame｜First Round of Audit Inquiry Reply (2026-04-16) https://static.sse.com.cn/disclosure/announcement/c/202604/002175_20260416_GUC4.pdf
Moore Threads｜First Round of Audit Inquiry Reply (2025-09-05) https://static.sse.com.cn/disclosure/announcement/c/202509/002098_20250905_EBZW.pdf
Hygon｜Prospectus (Registered Draft, 2022-06-22) and First Round of Audit Inquiry Reply (2022-03-04) https://static.sse.com.cn/disclosure/announcement/c/202206/001043_20220622_ATXX.pdf https://static.sse.com.cn/disclosure/announcement/c/202203/001043_20220304_7DDI.pdf
#DeepChipAlliance #BayChipExpo #SemiconductorIndustryResearch #OpenAI #AIChips