The design complexity of semiconductor and AI systems is increasing exponentially, pushing the traditional R&D model—which relies on engineers manually operating tools and enduring lengthy simulation wait times—to its breaking point.
In July 2026, NVIDIA announced major advancements during the DAC 2026 conference and unveiled a disruptive solution. On the hardware front, the Vera CPU, optimized specifically for EDA, delivers the underlying computing power. On the software front, the expansion of the NVIDIA Agent Toolkit, which integrates PhysicsNeMo and the new CUDA-X libraries, fully unleashes the potential of "autonomous AI engineers." A chip design revolution driven by AI agents is officially ignited.
Image source: NVIDIA
NVIDIA Agent Toolkit Integrates the PhysicsNeMo and CUDA-X Libraries
NVIDIA announced the expansion of the NVIDIA Agent Toolkit for the engineering domain. The core mission of this toolkit is to help developers build specialized engineering AI assistants that connect domain-specific tools, models, and data.
In this expansion, the architecturally restructured NVIDIA PhysicsNeMo library empowers AI agents with robust "AI physics skills." It enables agents to train and deploy customizable AI physics models for complex design and simulation tasks, and directly translate model architectures into directly callable tools within engineering workflows, breaking free from the time constraints of traditional numerical simulations.
Meanwhile, underlying compute acceleration has also undergone a comprehensive upgrade.
Making its debut, the NVIDIA cuISS (CUDA Iterative Sparse Solver) is designed for flexibility and high performance on GPUs. Leveraging composable solvers and preconditioning techniques, it assists developers in building scalable, production-grade simulation engines to accelerate the solving of large sparse linear systems in physics and engineering simulations.
Additionally, the NVIDIA cuDSS (CUDA Direct Sparse Solver) is specifically designed to accelerate the solving of core large, complex sparse linear systems in Electronic Design Automation (EDA) and scientific simulations, providing high performance and numerical robustness for critical workflows such as device, circuit, and system simulations.
Finally, NVIDIA cuEST (CUDA Electronic Structure Theory) introduces high-precision quantum chemical simulations into agent engineering workflows, enabling Density Functional Theory (DFT) and post-DFT methods to be integrated at scale into future production workflows.
A Bidirectional Hardware-Software Closed Loop: Using NVIDIA CPUs to Build Future NVIDIA Chips
Chip design agents exhibit a specific pattern during operation, frequently shuttling data between "GPU inference" and "CPU-intensive orchestration, simulation, and verification." Therefore, GPU acceleration alone is insufficient; critical EDA workloads (such as logic simulation and formal verification) remain highly dependent on the CPU's fast single-core performance, efficient memory system, and robust throughput capabilities.
To completely break through this bottleneck, NVIDIA introduced the next-generation Vera CPU, which has been fully deployed in internal EDA workflows.
Vera is equipped with 88 custom NVIDIA Olympus CPU cores, configured with an efficient LPDDR5X memory subsystem, and utilizes the second-generation NVIDIA scalable coherent interconnect architecture. Unlike the industry's common core-stacking approach, it focuses on single-core efficiency and memory bandwidth as its core optimization targets, providing sustained, stable, low-latency operation in engineering-intensive computing and massive regression testing tasks.
Initial tests show that, under the same core count configuration, the Vera CPU significantly boosts the performance by 1.5x for the two most compute-intensive applications in modern chip design: the formal verification platform Cadence Jasper and the functional verification solution Synopsys VCS.
Moving forward, NVIDIA plans to build upon Vera to introduce the next-generation Rosa CPU powered by NVIDIA Rigel cores, continuing to deliver targeted optimizations for leading EDA applications.
Software Giants Are Leveraging the NVIDIA Agent Toolkit to Build Autonomous AI Engineers
Global semiconductor and software giants are comprehensively adopting NVIDIA's accelerated computing and agentic AI technologies to advance autonomous engineering workflows in chip design, verification, packaging, and system design.
In agentic workflows, RTL (Register Transfer Level) coding is critical to the success or failure of a chip. Supported by ACE-RTL, a hardware design agent launched by NVIDIA Research, NVIDIA Nemotron 3 Ultra excels in comprehensive Verilog design problem benchmarks, taking the lead in agentic RTL coding tasks among open models.
As an open model, it not only delivers leading accuracy and efficiency but also supports post-training on proprietary enterprise data and can be deployed locally or on-premises, providing strong controllability, customization capabilities, and data privacy assurance for enterprises building customized AI agents.
Currently, developers can quickly get started and experience these capabilities through Cadence's Harness, Synopsys's fully autonomous, long-running agents designed for design verification and analog and mixed-signal workflows, Siemens' Questa One intelligent verification agent toolkit, and the Hugging Face platform.
From the perspective of product deployment, major industry leaders have demonstrated remarkable quantitative gains in practical applications.
Cadence combines NVIDIA technology with its newly launched Cadence AuraStack AI Super Agent and Millennium M2000 platform to autonomously drive advanced packaging and PCB design from exploration to signoff, achieving up to a 20x improvement in multiphysics performance. Meanwhile, its formal verification platform, Cadence Jasper, is being optimized for the NVIDIA Vera CPU.
Synopsys leverages the NVIDIA Agent Toolkit, NIM, Nemotron open models, NeMo Gym libraries, and NemoClaw blueprints, combined with Synopsys Agent Engineer, to build autonomous agentic workflows. It can autonomously execute simulation setup and pre/post-processing for complex GPU thermal design optimization using Ansys Icepak. Additionally, its functional verification solution, Synopsys VCS, is also being optimized for the NVIDIA Vera CPU to enhance verification throughput.
Siemens is combining NVIDIA NeMo Gym, Nemotron open models, and CUDA-X libraries with the Siemens Fuse EDA AI agent to accelerate library characterization speeds by more than 10x in the Siemens Solido Characterization Suite, while reducing token costs to less than one-tenth of the original.
Samsung is also utilizing NVIDIA cuLitho and CUDA-X libraries to boost computational lithography performance by up to 20x, and applying PhysicsNeMo for chip-level thermal stress analysis.
Furthermore, ChipAgents is leveraging this toolkit to fine-tune Nemotron models for complex workflows such as debugging and formal verification.
Conclusion
In the past, many engineers' careers were tied to the tedious operations of specific EDA tools; in the future, with the assistance of NVIDIA's autonomous engineering agent ecosystem, engineers will be liberated and elevated to "system-level thinkers and designers" who oversee the big picture.
They will focus on higher-dimensional architectural innovation, while tedious tuning, verification, and debugging will be fully entrusted to trusted autonomous AI engineers. This automated iterative model—defined by software, accelerated by hardware, and closed-looped by agents—is becoming the standard methodology for high-compute chip development.