"MIPS fully transitioned to RISC-V in 2021 and, following its parent company GlobalFoundries' acquisition of ARC, became the company with the most RISC-V IP globally," said Li Yong, Head of Business Development for MIPS China, at the "RISC-V and Physical Intelligence Forum" co-hosted by the Shanghai Open Processor Industry Innovation Center (SOPIC) and VeriSilicon.
Figure | Li Yong, Head of Business Development for MIPS China
The deployment of Physical AI is encountering a realistic watershed: model complexity is surging, while the boundaries of power consumption, latency, and cost remain strictly constrained.
Facing this challenge, Li Yong believes that peak TOPS cannot solve the problem. The key lies in effective inference per unit of power consumption, as well as bridging the often-broken link between software and chips.
Against this backdrop, MIPS's approach is to leverage its 40-year foundation in embedded computing on the open architecture of RISC-V. Li Yong mentioned that after joining the GlobalFoundries ecosystem and integrating Synopsys' ARC business, MIPS now holds 41 processor and AI cores, covering a complete product portfolio from MCU (Microcontroller Unit) to application processors and NPU. The significance of this move lies in its ability to make differentiated customizations for different physical scenarios on the same instruction set foundation, rather than starting from scratch every time the scenario changes.
The S8200 is a product of this approach. It integrates scalar, vector, matrix, and data movement engines within a single cluster. The most direct result is that AI inference can be performed independently without frequently turning to the main CPU for resources. The computing power is adjustable from 0.1 to 100 TOPS, not by stacking cores, but by reconstructing the data flow at the ISA level through the outer product matrix architecture. Under a 64x64 matrix, the data loading volume is reduced by 32 times compared to traditional inner product solutions. This is directly reflected in power consumption and area—achieving an energy efficiency of over 30 TOPS/W without relying on sparsity, which means more tangible benefits under real-world operating conditions.
Hardware multithreading technology reduces TFLM inference latency by 40%. With the RVV 1.0 vector width reaching 1024 bits, supplemented by custom instructions and BF16/INT4/FP4 data formats, it provides flexible support for spatio-temporal perception models such as vision, point cloud, and BEVFormer.
More critically, it is the integration between software and hardware. Li Yong revealed that before tape-out, Atlas Explorer can run workload simulations. Architects can directly see the impact curve of SRAM capacity changes on the ResNet50 frame rate, thereby making trade-offs between performance and cost rather than making decisions based solely on experience. The compiler, based on MLIR, performs global optimization at the computational graph level instead of adapting operator by operator, which saves a lot of trouble in operator compatibility in the later stages.
In actual scenarios, the S8200 runs BEVFormer to process 8-channel camera inputs. With an inference throughput of 15 FPS and a forward-looking latency of <33ms, it meets the strict window requirements for spatio-temporal fusion perception in L2+ ADAS.
Global shipments of RISC-V are growing from 6.9 billion units to 36 billion units, and the domestic market size has tripled in five years. MIPS is now extending RISC-V from its embedded DNA to the main battlefield of high-performance Physical AI, using the certainty of software-hardware synergy to dissolve the uncertainty of fragmented scenarios.