This column provides irregular interpretations of testing industry standards. You are welcome to post the testing standards you want to learn about or ask questions regarding standards and testing in the comments section, and Keysight Technologies test engineers will provide answers. As a global leader in test and measurement technology, Keysight Technologies has long been committed to promoting technology standardization and the refinement of testing methods, providing the industry with comprehensive test solutions.
Original Author: Victor Sanchez-Rico Guerra, Keysight Technologies' representative to the MIPI Alliance for MIPI C-PHY/D-PHY/M-PHY standards
Translation and Proofreading: Marketing Department and Technical Support Department of Keysight Technologies (China) Co., Ltd.
What You Will Learn
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- A brief overview of the evolution of C-PHY™ and D-PHY™
- Changes introduced by the 18-Wirestate Mode in C-PHY™ 3.1
- Changes introduced by the Embedded Clock Mode (ECM) in D-PHY™ 3.6
- How future connectivity solutions will reduce wiring in compact systems
- Why C-PHY™ and D-PHY™ continue to co-evolve within a shared ecosystem
- New conformance testing and verification challenges brought by the latest Physical Layer (PHY) evolution
- How Keysight solutions empower next-generation MIPI verification
Introduction
As high-resolution sensors, advanced displays, machine vision, and AI-assisted processing become more prevalent, the bandwidth demands on camera and display interfaces continue to grow. Meanwhile, system designers face pressure to reduce power consumption, shrink connector sizes, lower wiring complexity, and minimize overall packaging. These requirements are particularly evident in smartphones, AR/VR devices, automotive vision systems, AI PCs, and emerging Physical AI systems such as humanoid robots and drones.
MIPI® C-PHY™ and MIPI® D-PHY™ have become the core Physical Layer (PHY) technologies connecting image sensors, displays, and processors. Specifically, CSI is used for sensors and DSI for displays, and both protocols can operate on either PHY. Although these two technologies adopt different signal transmission architectures, their evolution goals are entirely identical: transmitting more data while reducing the number of physical interconnects required by the system.
Therefore, the latest evolution of these PHYs is not only to achieve higher baud rates but also to enhance the overall system efficiency by improving bandwidth utilization and reducing power consumption.
A Brief History of C-PHY™ and D-PHY™ Evolution
The following table summarizes the key evolutionary stages related to current and future PHYs:
| Physical Layer (PHY) | Generation | Maximum Data Rate | Core Innovation | Significance |
| C-PHY™ | 1.x/2.x | 6.5 GSps (14.8 Gbps) per trio | 6-Wirestate operation | Enables efficient sensor and display connections using three-wire trios. |
| C-PHY™ | 3.1 | 7 GSps (24.8 Gbps) per trio | 18-Wirestate Mode and Alternate Low Power (ALP) Mode | Increases the number of bits per baud without adding wires, thereby improving effective throughput. |
| C-PHY™ | Future Evolution | Multi-device support | Reduces the number of physical links in compact multi-device systems. | |
| D-PHY™ | 1.x/2.x | 4.5 Gbps (Standard CH) per lane 6.5 Gbps (short CH) |
Forward Clock Mode (FCM) | Adopts a dedicated clock channel, featuring a simple and robust architecture. |
| D-PHY™ | 3.6 | 9 Gbps (Standard CH) per lane (FCM / ECM) 11 Gbps (short CH FCM) |
Embedded Clock Mode (ECM) and higher symbol rates | Eliminates the dedicated clock channel by embedding timing information in the data stream. |
| D-PHY™ | Future Evolution | Multi-device support and higher symbol rates | Reduces wiring at the system level for multi-endpoint architectures. |
Although C-PHY™ and D-PHY™ adopt different signal architectures, their evolution is closely intertwined. Many devices implement a Combo PHY architecture. This provides system designers with great flexibility, allowing a single device to support a wide range of camera and display configurations. It also means that both PHYs must share a common ecosystem defined by protocol-supported channel definitions.
What Are the New Features in C-PHY™ 3.1?
C-PHY™ utilizes three-wire trios instead of traditional differential data lanes. This allows information to be encoded across three wires, thereby improving efficiency and reducing the number of wires for a given throughput.
C-PHY™ 3.1's core upgrade is the 18-Wirestate Mode. In previous generations, each wire used three signal levels, resulting in six valid wirestates. C-PHY™ 3.1 expands this to seven signal levels and eighteen valid wirestates. This increases the coding efficiency from approximately 2.28 bits per baud to about 3.55 bits per baud, meaning that at the same baud rate, the amount of transmitted information increases by approximately 55%.
Transitioning to the 18-Wirestate Mode also necessitates the introduction of the Alternate Low Power (ALP) Mode. This is not an optional architectural scheme: supporting seven signal levels requires a higher High-Speed (HS) amplitude, which overlaps with the Legacy Low Power signal region. Consequently, legacy low-power operation can no longer work in conjunction with 18-wirestate signals, making ALP mode mandatory. Therefore, the C-PHY™ 3 PHY must operate either in "6-Wirestate Mode with Legacy Low Power (LLP)" or in "18-Wirestate Mode with ALP," with no other combinations allowed.
Figure 1: Example of a C-PHY™ 3.1 18-Wirestate Mode eye diagram generated using Keysight instruments
What Are the New Features in D-PHY™ 3.6?
Traditional D-PHY™ implementations adopt the Forward Clock Mode (FCM), where a dedicated clock lane transmits in conjunction with one or more high-speed data lanes. Although this architecture is robust and widely used, the clock lane itself consumes system resources and connection pins.
D-PHY™ 3.6 introduces the Embedded Clock Mode (ECM). Instead of transmitting a separate clock signal, this mode uses 128b/132b encoding to embed timing information into the data stream, which is then recovered by the receiver. This eliminates the dedicated clock lane, reducing wiring requirements while retaining the traditional NRZ signaling method used in D-PHY™.
Furthermore, compared to previous generations, D-PHY™ has enhanced its data rate capabilities. The operating rate specification for standard lanes has reached up to 9 Gb/s. Forward Clock Mode (FCM) will continue to be supported, and in short-lane applications, it can operate at rates up to 11 Gb/s. These higher rates, coupled with ECM's reliance on clock recovery, make lane behavior, jitter performance, and timing recovery new focal points for verification.
Figure 2: D-PHY™ waveform simulation and analysis using Infiniium XR8. From left to right, top to bottom: raw waveform, clean eye diagram, eye diagram with embedded channel and package models, and equalized eye diagram
Future Directions: Multi-Device Connectivity and Higher Data Rates
Future versions of C-PHY™ and D-PHY™ are expected to introduce Multi-device Connectivity. Traditional camera and display architectures are typically based on Point-to-Point links. While this mode is simple, the challenges grow significantly when a compact product integrates multiple displays, cameras, or sensors.
AR glasses are a typical example. Multiple high-speed connection lines must pass through the temple hinges or other areas with severely restricted mechanical space. Each additional high-speed link increases the number of cables, connection complexity, mechanical stiffness, and concerns about long-term reliability. The multi-device architecture aims to reduce the number of physical interconnect cables by allowing various endpoints to share connection resources more efficiently.
Figure 3: Conceptual diagram illustrating how multi-device connectivity reduces the number of high-speed links passing through the restricted area of glasses hinges
Beyond multi-device connectivity, the market's pursuit of higher data rates continues unabated. Camera systems are the obvious driver: higher-resolution sensors, faster frame rates, multi-camera architectures, and Physical AI systems have significantly increased the amount of data that must be transmitted from the sensor to the host.
Conformance Testing and Verification Challenges in the Evolution
In C-PHY™ 3.1, the transition from the 6-Wirestate Mode to the 18-Wirestate Mode introduces new challenges for signal quality verification due to the increased number of levels. With more levels compressed into the same signal, characterizing the Transmitter requires more careful examination of linearity, eye opening, and overall waveform integrity across the expanded signal space.
For C-PHY™ 3.1 transmitter conformance testing, key measurement metrics include RLM (Ratio of Level Mismatch) and 18-Wirestate Mode eye diagram measurements. These metrics are used to evaluate whether multiple signal levels maintain sufficient linearity and whether the eye diagram retains adequate margin, making signal quality analysis a core aspect of verifying 18-Wirestate operation. For characterizing Receiver attributes, clock recovery behavior and jitter tolerance remain critical considerations as the PHY continues to evolve.
For D-PHY™, verification efforts must still start from the basics: signal quality, timing margin, jitter, and lane behavior. ECM mode places greater emphasis on clock recovery, jitter analysis, and stress testing, bringing D-PHY™ verification methods closer to other standards that have adopted embedded clocks. Although the underlying technology may seem familiar, higher data rates make margins extremely tight, leaving almost no room for error.
Keysight Solutions Empower Next-Generation MIPI Verification
Verifying these PHYs is by no means a single-dimensional issue. Receiver testing requires precise and calibrated waveform generation capabilities; transmitter testing demands clean signal acquisition and analysis capabilities; and conformance testing requires automation, repeatability, and strict alignment with standards. The role of Keysight is to connect these pieces into practical verification workflows through active participation in the development of MIPI standards.
On the Signal Generation Front
The Keysight M8195A Arbitrary Waveform Generator (AWG) remains the core platform for MIPI receiver verification and cutting-edge exploration. Combined with IQTools software, it can generate advanced C-PHY™ and D-PHY™ waveforms for technology exploration and early verification work. This offers a significant benefit to customers—investment continuity: the same AWG used for previous PHY generations now remains the reference platform for updated PHY modes and future standard evolution. This helps customers fully leverage existing test assets while preparing for emerging technologies.
Figure 4. Example of generating advanced MIPI C-PHY™ and D-PHY™ waveforms using the IQTools waveform generation tool with the M8195A Arbitrary Waveform Generator (AWG)
On the Transmitter Characterization Front
The top priority is to capture the signal clearly. As signal levels get closer together (which is particularly evident in C-PHY™ 3), the oscilloscope's noise floor becomes more critical than ever. Next, clock recovery and CTLE (Continuous Time Linear Equalization) are required for the 18-Wirestate. This is exactly where the Infiniium series oscilloscopes excel.
For current transmitter conformance verification, Keysight provides solutions such as the D9330DPHC for D-PHY™ Forward Clock Mode testing. As C-PHY™ and D-PHY™ continue to evolve, the continuous advancement of test and measurement science will ensure support for increasingly stringent verification requirements.
Figure 5. Example of the D9330DPHC transmitter conformance automated test software workflow for D-PHY™ Forward Clock Mode (FCM) verification
Conclusion
C-PHY™ and D-PHY™ continue to evolve through different technical pathways to address the growing bandwidth demands of camera and display systems. The 18-Wirestate Mode improves bandwidth efficiency, ECM mode introduces a more efficient link architecture through embedded clock recovery, and future multi-device architectures extend these advantages to the system level. These transitions bring entirely new conformance testing requirements and verification challenges. With advanced instruments, software automation, and deep standard expertise, Keysight is helping customers confidently embrace the next generation of MIPI imaging technology.