On October 12, Lanxin Computing (Shenzhen) Technology Co., Ltd. completed its Series B financing, with a scale of nearly CNY 2 billion. Existing shareholders Shen Chuang Tou, Huakong Fund, and Longqiu Capital continued to increase their investments. New investors include local guidance funds such as Su Guotou and Yueke Finance, industrial capital such as GigaDevice Semiconductor, and institutions such as Taiping Kechuang, Jianyin International, and Jiukun Chuangtou. The company stated that the funds will be directed towards three areas: advancing the mass production of RISC-V CPUs, iterating AI heterogeneous processors, and providing general computing solutions for telecom operators, financial institutions, and cloud service providers.
Prior to this round of financing, Lanxin Computing completed its angel round in December 2023, the Pre-A round in December 2024, and announced the completion of the Pre-A and Pre-A+ rounds in June 2025. During the same period, the Pre-A++ round was nearing its close and was completed in August 2025. In March 2026, the company completed three rounds of financing in one go: Series A, A+, and A++. In June of the same year, the Pre-B round of over CNY 300 million, exclusively invested by Longqiu Capital, was closed. Having raised funds for over ten rounds in just three years since its establishment, such capital density is uncommon among domestic chip startups.
Venture capital data shows that, based on October 2026, the predicted probability of the company's financing in the following two years is 77.16%.
| From Intel and Qualcomm to ByteDance, and Then Starting a Business
Founded in May 2023, Lanxin Computing is headquartered in Nanshan, Shenzhen, with branches or R&D centers in Beijing, Shanghai, Xi'an, Suzhou, and Hong Kong. The founder and CEO, Lu Shan, received his bachelor's degree from the Department of Automation at Tsinghua University and his Ph.D. in Electrical and Computer Engineering from Boston University. He subsequently worked on high-performance CPU and SoC (System on Chip) design at Intel and Qualcomm. In 2019, he joined ByteDance's chip team in San Diego, USA, where he was responsible for RISC-V and server chip projects, before leaving to start his own business in May 2023. CTO Jia Xinxia has 21 years of chip design experience and has previously worked at HiSilicon and Qualcomm. Core team members mostly come from international giants such as Intel and Qualcomm. The company claims the team possesses full-stack capabilities for data center-grade RISC-V CPUs.
| One Chip, Two Engines
The LX500 is the company's current core product. According to the company's definition, it is the world's first server-grade CPU that natively integrates RISC-V general-purpose computing and AI (Artificial Intelligence) inference on a single chip. It adopts a 48-core heterogeneous design: 32 high-performance cores handle high-throughput general-purpose computing, while 16 high-efficiency cores process lightweight workloads and undertake AI computing offloading. It integrates an on-chip AI engine with a peak performance of 75 TOPS (INT8), supporting multiple precision formats such as INT4/INT8/FP16/FP32. It is compatible with the RVV 1.0 vector extension and RVA23 specifications, supports CXL 2.0 on the memory side, and natively supports PCIe 5.0 at the interface.
Compared with the traditional discrete solution of "CPU plus independent AI acceleration card," the difference with the LX500 is that AI inference is completed directly inside the chip. Data does not need to be repeatedly transferred between the CPU, memory, and acceleration card, thereby reducing latency and deployment costs. This approach corresponds to the reality of the large model era: servers need to run both general-purpose businesses and inference workloads. If the two sets of computing power are split into two boards, communication overhead will become a bottleneck. Integrating both into a single chip is a solution to eliminate this overhead—of course, the trade-off is higher design complexity and greater difficulty in balancing both aspects in the architecture.
| From First Silicon to Complete System in Five Months
According to public reports, in February 2026, the LX500 was successfully taped out and powered on in one go, booting the Linux operating system. In May, the company completed the adaptation of the "RISC-V + BC-LINUX" full-stack integration solution with the China Mobile Cloud Capability Center. In July, the Lenovo Wentian WR5219 G5 equipped with the LX500 rolled off the production line at the Hefei Lianbao factory. The company claims this is the world's first mass-produced RISC-V + AI server. The interval from the chip's first silicon to the complete system rolling off the production line was about five months, at a time when the company had been established for less than three years.
In terms of verification, the on-chip AI engine of the LX500 has successfully run the 128K long-context quantized version of the trillion-parameter Kimi K2.6, as well as the 35-billion-parameter Qwen3.6-35B, and has been adapted for mainstream models such as DeepSeek and Hunyuan. On the customer side, the company disclosed that it has received orders for over 200,000 chips from Lenovo, China Mobile, Tencent Cloud, and others. It has also reached strategic cooperation with Lenovo Group, China Mobile, Tencent Cloud, and Shiji Hulian. The scenarios cover the computing power foundation for telecom operators' cloud networks, elastic computing power supply for data centers, as well as intelligent risk control and quantitative trading for financial institutions. In addition, the company has established a RISC-V + AI integrated CPU joint innovation laboratory with Lenovo, and is co-building a domestic intelligent computing foundation with the financial technology company Kaimaieruide.
| RISC-V at the Table: How Many Steps Left?
RISC-V has long been regarded as a choice for the IoT (Internet of Things) and embedded fields, and whether it can enter data centers has always been a focus of debate.
It is open and customizable, which can reduce reliance on instruction set architecture licenses and has a natural advantage in promoting independent technological iteration. However, openness does not mean there are no barriers—software compatibility, system stability, application migration, and ecosystem maturity are all unavoidable thresholds in high-performance server scenarios. The frequent moves by organizations such as the RISC-V Working Committee and local semiconductor industry alliances in recent years also indirectly indicate that ecosystem construction is still in its early stages.
Lanxin Computing does not directly compete with x86 and ARM in general-purpose CPUs, but instead bets on the incremental scenario of AI inference. The smart part of this strategy is avoiding direct competition with mature ecosystems. The risk, however, lies in the fact that the hardware track for AI inference is already crowded with GPU manufacturers, dedicated acceleration card companies, and cloud vendors' self-developed chips. For RISC-V to gain a share of this market, it relies not only on architectural advantages but also on the software stack and customer relationships.
First silicon is just the first step; scaled application must also pass the tests of performance testing, ecosystem adaptation, and customer verification. The founder previously revealed that the task for 2026 is to start batch testing simultaneously in China and the United States, striving to achieve large-scale mass production in 2027. The delivery pace over the next two years will provide the answer to whether this path can succeed.
The information in this article is compiled from public reports by Cai Lian She's SSE STAR Market Daily, Lieyunwang, Nanfang Dushi Bao, etc., and is for reference only and does not constitute investment advice; relevant data is subject to the official disclosure of the enterprises.