Xindongxi reported on November 4 that, according to Qiming Venture Partners, Beijing-based intelligent video chip company Transtreams recently completed a Series B financing round of CNY 1 billion. According to the corporate information platform Qichacha, this round was jointly led by Qiming Venture Partners, Zhaohui Capital, and Yizhuang Industrial Investment, with follow-on investments from CDH BaiFu, Jinduo Investment, Haitong Kaiyuan, and other institutions. Existing shareholders such as Shunxi Fund and Jiuzhi Capital also participated in additional investments. The raised funds will be used for next-generation chip R&D and mass production, as well as global market expansion.
Founded in March 2024 and headquartered in Daxing District, Beijing, Transtreams specializes in developing dedicated computing chips and hardware products for intelligent video processing and generative video (AIGV) scenarios. The company was incubated within Kuaishou's Heterogeneous Computing and Chip Business Unit. Its core business involves providing underlying computing power support for multimodal large models in applications such as intelligent video and AIGV.
The founder, chairman, and CEO of the company, Liu Lingzhi, holds a PhD from Shanghai Jiao Tong University and is a postdoctoral researcher at the University of Washington. He previously served as Vice President of Kuaishou Group and held core technical management positions at companies including Huawei and Intel. Transtreams's core team primarily comprises graduates from top global universities such as Tsinghua University, Peking University, Stanford University, and Carnegie Mellon University, with work experience at international tech giants like Huawei, Intel, Qualcomm, Google, Apple, and Microsoft. The team averages 15 years of experience in chip design, software algorithms, and infrastructure, having led the tape-out and mass production of more than 10 chips. Qichacha data shows that Transtreams has completed six rounds of financing since its establishment in 2024.
Looking at the financing history, multiple existing shareholders have continued to invest in Transtreams. In June this year, the company completed an A+ round of financing worth several hundred million yuan, led by Qifu Capital, with follow-on investments from Shunxi Fund, Beijing Sci-Tech Innovation Fund, Jiuzhi Capital, and others. In July and October 2025, it completed two rounds of Series A financing, involving investors such as Shouyi Sci-Tech Innovation Mother Fund, Wanyin Asset, Shunxi Fund, Yizhuang Industrial Investment, and Jiuzhi Capital. In June 2024, Transtreams completed its angel round, invested by Shunxi Fund.
Addressing the computing power demands of video processing and generative AI, Transtreams is pursuing two parallel technological routes: one based on the SL200 chip to build a series of products, and the other focused on developing next-generation 3D near-memory architecture and DiPU technology. The core technology of Transtreams's SL200 is its self-developed CAE (Content-Adaptive Encoding). It can real-time analyze scene, texture, and motion characteristics of video frames on-chip, dynamically optimizing bitrate allocation, prediction modes, and compression strategies accordingly.
The core objective of this mechanism is to significantly reduce redundant bitrates while preserving key visual information as much as possible, thereby achieving a balance between encoding efficiency, image quality, and power consumption. According to Transtreams's official account, the SL200 is China's first dedicated SoC chip integrating intelligent video processing, AI inference, and multi-core CPU. A single chip can handle 36 channels of high-definition video tasks, with a failure rate as low as less than one in ten thousand.
In May this year, the company disclosed that in the MSU2025 World Codec Competition hosted by Moscow State University, its self-developed intelligent video processing chip SL200 ranked first in all sub-tracks of commercial encoders (1080p@30/60/120/240fps). Compared to NVIDIA's latest AV1 encoding solution (NVIDIA NVENC AV1 5060 Ti), the SL200 improved compression efficiency by 30%~35%.
Based on the SL200 chip, Transtreams has launched various product forms, including the SL200-Nano and SL200-Pro intelligent video acceleration cards, and the AIBOX edge computing integrated box, covering scenarios such as large-scale cloud transcoding, edge intelligent processing, and end-side video analysis.
Targeting scenarios such as AIGV, world models, embodied intelligence, and autonomous driving, Transtreams has pioneered a latency-deterministic software-hardware solution encompassing both computational and physical architectures, based on the RISC-V ecosystem.
In terms of computational architecture, the solution includes the DiPU processor, LUCA architecture, and LUCAS software stack, driving the evolution from traditional GPGPU to DiPU. Addressing the pain points of unpredictable memory access latency and low computing power utilization caused by instruction-driven traditional GPUs, DiPU adopts dataflow-driven spatial computing. By having the compiler fully take over storage and scheduling during compilation, it achieves "triple determinism" in latency, timing, and bandwidth.
In terms of physical architecture, the solution uses a self-developed 3D near-memory architecture, combining domestic 3D stacking and hybrid bonding technologies. Through NUMA direct connection, it achieves local access latency of less than 2 nanoseconds.
Currently, Transtreams's next-generation chip based on this architecture completed tape-out and successful return in April 2026, with scale shipments expected in 2027. This product primarily targets AI video production processes and is poised to become China's first 3D architecture chip for large-scale commercial use in internet data centers.
Conclusion: Differentiated Computing Power Demand Drives Chip Architecture Towards Segmentation and Specialization
As AI computing power demand continues to grow, the approach of simply stacking general-purpose chips faces limitations in cost and energy efficiency. Chip design is shifting from broad-scenario general architectures to segmented solutions tailored for specific workloads.
In high-computing-power scenarios such as video processing and generative AI, pursuing high energy efficiency ratios and deterministic latency through bottom-layer architectural innovations like dedicated SoCs and 3D near-memory has become a concrete path to address growing computing demands. Future computing power competition will not only pursue peak performance but also prioritize precise control and deep adaptation of computing costs for specific application scenarios.