The AI (Artificial Intelligence) story of Baidu written yesterday is closely related to Qi Lu. Kunlunxin, which is about to go public, also originated from Qi Lu's vision. At the weekend chip breakfast meeting, a friend asked about the history of Intel's acquisition of Altera. It occurred to me that this event is also closely related to Qi Lu, so it is a good time to sort it out.
In April 2025, a piece of news left the semiconductor industry in deep regret.
Intel announced that it would sell a 51% stake in its FPGA (Field-Programmable Gate Array) company Altera to Silver Lake Partners at a valuation of $8.75 billion. Recall that when Intel acquired Altera in 2015, it cost a full $16.7 billion. In ten years, the valuation has been halved.
This is not a simple case of a botched "buy low, sell high" strategy. Behind this lies a decade-long battle over computing power routes in data centers. GPU (Graphics Processing Unit), FPGA, and ASIC (Application-Specific Integrated Circuit)—three technical routes were each bet on, and ultimately, NVIDIA's GPU won.
But in the era of AI inference, the story of FPGA may not be over yet.
I. The Catapult Project Strongly Promoted by Qi Lu
In 2012, at Microsoft headquarters, a crucial meeting was underway.
Doug Burger, an engineer at Microsoft Research, was standing in front of then-CEO Steve Ballmer, trying to persuade him of an idea that sounded incredible: Microsoft should build its own programmable chips. Ballmer immediately dismissed the idea.
Those present later recalled that Ballmer's reaction could roughly be translated as: Microsoft has spent forty years building Windows and Office, and now you want us to make chips? How is this any different from Coca-Cola announcing it will make shark fin soup?
But just as the atmosphere froze, another person spoke up.
Qi Lu, then head of the Bing search engine, had been secretly collaborating with Burger's team for two years. He told Ballmer: This is not a question of "whether to do it or not"—"his team has already started."
It was this sentence that saved the Catapult project.
Two years later, in 2014, Microsoft published a paper at ISCA, the top conference on computer architecture. The data in the paper shocked the entire industry—
In the document ranking computation of the Bing search engine, using FPGA for hardware acceleration increased throughput by 95% and reduced system latency by 29%. The additional power consumption per FPGA was less than 25 watts, and the total cost increase did not exceed 30%. Moreover, this was compared to Microsoft's deeply optimized pure software solution.
In other words, this was not "optimization from scratch," but rather, on the basis of "having already squeezed the maximum performance out of the CPU," FPGA pushed the ceiling up by nearly double. Since the birth of the world's first FPGA product in 1985, FPGA applications have gradually expanded from digital signal processing and high-speed serial transceivers to embedded processors. FPGAs have been widely used in microelectronic and electrical fields such as communications, consumer electronics, industrial control, and test and measurement, but have rarely been applied in large data centers.
This paper was the first professional paper in the true sense to detail the development and large-scale deployment of FPGAs by Internet giants. Before this, FPGAs were the exclusive toys of hardware companies. After this, Google, Amazon, Baidu, and Alibaba—all Internet giants—began to seriously consider: whether to deploy FPGAs in data centers.
Microsoft took immediate action. By 2016, Microsoft had deployed FPGA acceleration cards in 5,670 servers across 15 countries on five continents. In 2017, it launched the Brainwave project, expanding the application of FPGAs from search to deep learning.
Notably, except for the initial prototype validation phase of the project, Microsoft subsequently adopted Intel (Altera) FPGA chips entirely. Microsoft suddenly became Intel's largest FPGA customer.
The "Wintel Alliance" of the past, in the post-PC era, seemed to be finding a path to rebirth through FPGAs.
In September 2014, Baidu quickly followed suit, announcing that it would use FPGA technology in its own data centers. Qi Lu left Microsoft in 2016 and immediately joined Baidu as Vice President, which also seems to have a deep connection with this Catapult project.
II. Three Paths Set Off Simultaneously, No One Knows Who Is Right or Wrong
Around 2015, the data center acceleration market was a true "Three Kingdoms" situation.
NVIDIA promoted the GPU route. Google bet on the TPU (Tensor Processing Unit) route (a type of ASIC custom chip). Microsoft developed the FPGA route.
The three routes each had their own rationale.
GPU: A Swiss Army Knife.
GPUs were originally designed for game graphics rendering, but after the great success of AlexNet using GPUs to train neural networks in 2012, people found that this large-scale parallel computing architecture was naturally suited for AI. NVIDIA built a powerful software ecosystem around CUDA—4 million active developers, with native support for all mainstream frameworks. The drawback is that it is expensive. A single H100 sells for $40,000, and its power consumption is massive.
FPGA: A Set of LEGO Bricks.
FPGAs are "field-programmable"—after the chip is manufactured, engineers can redefine its internal logic connections through software. This means extreme flexibility: today it is used to accelerate search sorting, tomorrow it can be reconfigured for network protocol offloading, and the day after it can run AI inference. Microsoft's Catapult proved that this route is feasible. The drawback is the high development threshold—you need hardware engineers to write Verilog code; it cannot be done just by tuning PyTorch.
ASIC/TPU: A Customized Screwdriver.
Google launched the first-generation TPU in 2015, specifically optimized for TensorFlow computations. Once an ASIC is taped out, its functions are fixed and cannot be changed, but this brings an extreme energy efficiency ratio. In 2015, Google found that the demand for neural network inference in data centers was soaring, but GPU efficiency was insufficient. Thus, the TPU was born. The drawback is the worst flexibility—if the model architecture changes, the chip might become useless.
The situation at that time was very much like the early days of the mobile Internet: Symbian, Windows Mobile, iOS, and Android. All players were betting, and no one knew who would win.
Intel did not choose just one route, but tried to merge two routes into one—CPU+FPGA.
III. Two Sky-High Acquisitions, Two Completely Different Outcomes
On June 1, 2015, Intel announced the acquisition of Altera for $16.7 billion. This was the largest acquisition in Intel's history.
The logic of the acquisition sounded very reasonable: deeply integrate Altera's FPGA technology with Intel's Xeon processors to provide data center customers with an integrated "CPU+FPGA" solution. Intel drew a two-step roadmap at the time: the first step was to package the CPU and FPGA together. The second step was to integrate both onto the same silicon die.
At the same time, another giant in the FPGA industry was also being watched.
In October 2020, AMD announced the acquisition of Xilinx in an all-stock transaction, initially valued at $35 billion. When the transaction was completed in February 2022, due to a significant increase in AMD's stock price, the final value reached $49.8 billion.
The two acquisitions were five years apart, the amounts differed by nearly three times, and the final outcomes were worlds apart.
Intel + Altera: An Unfulfilled Promise.
In 2018, Intel produced co-packaged samples of Xeon Skylake + Altera Arria 10. This was the world's first CPU+FPGA co-packaged chip. But what happened next? No mass production. It remained stuck at the sample stage forever.
Worse still, after Altera was acquired, a series of problems were exposed.
First, when the Altera team used Intel's in-house EDA tools within Intel, they found that these tools were optimized for CPU design. CPU logic is dense and regular, whereas FPGA logic is sparse and filled with a massive amount of interconnects. The design requirements for the two types of chips are almost opposite. The tool mismatch directly led to severe delays in product development. Altera's Agilex 7 series was a full two years behind its competitor Xilinx's 7nm Versal.
Second, the Altera business has always been a "nobody" within the giant ship of Intel. Its annual revenue was less than $2 billion, accounting for only 3%-4% of Intel's overall revenue. It could not rank high in resource allocation or strategic priority.
Then came a chain reaction: the cancellation of Omni-Path interconnect technology (2019), the cancellation of the Nervana AI accelerator (2020), and the cancellation of Optane persistent memory (2022). Every piece of the CPU+FPGA ecosystem puzzle was breaking apart one by one.
Ten years later, Altera's fiscal year 2024 revenue was $1.54 billion, with a GAAP operating loss of $615 million. The $16.7 billion buy-in price turned into an $8.75 billion sell-out price.
AMD + Xilinx: A Rising "Adaptive Computing" Star.
AMD's integration took a completely different path. Lisa Su did not simply "swallow" Xilinx; instead, she let former CEO Victor Peng continue to lead the Adaptive and Embedded Computing Group, retaining Xilinx's brand, channels, and product lines.
More importantly, before being acquired, Xilinx already had a killer product—the Zynq series.
IV. The Paradigm-Shifting Impact of Zynq
In 2010, Xilinx did something that seemed very radical at the time: integrating an ARM processor directly into an FPGA chip.
The product was named Zynq. Before this, FPGAs and CPUs were two independent chips communicating via external buses, resulting in high latency, high power consumption, and complex design. Zynq integrated the dual-core ARM Cortex-A9 processor and FPGA programmable logic onto the same silicon die, achieving "seamless integration."
How advanced was this idea? Even today, Intel and AMD are still telling the story of CPU+FPGA heterogeneity—yet Xilinx achieved it over a decade ago and sold it very well.
The Zynq UltraScale+ MPSoC is currently the main product. A single chip integrates a quad-core Cortex-A53 (running Linux), a dual-core Cortex-R5 (for real-time control), a GPU, and FPGA programmable logic. BMW's autonomous driving system uses this chip for sensor fusion—real-time processing of data from LiDAR, cameras, and millimeter-wave radar, with latency controlled within 10 milliseconds. Industrial robots use it for an integrated motion control + visual inspection solution, replacing the traditional "PLC + dedicated vision chip" architecture, reducing costs by 20% and shrinking the volume by 40%.
Moving up, there is the Versal platform. Xilinx calls it ACAP—Adaptive Compute Acceleration Platform. Built on a 7nm process, it features a built-in AI Engine (an array of AI vector processors), specifically optimized for large model inference.
Therefore, when AMD completed the acquisition in 2022, what it obtained was not a "traditional FPGA supplier," but an "adaptive computing platform" that already had a complete product matrix of ARM+FPGA+AI Engine.
And what was Altera doing?
During the years it was acquired by Intel, Altera's resources were scattered. While Xilinx was pushing Zynq and Versal, Altera was slow to update even its own SoC (System on Chip) product line. By the time the Agilex 5 series was released in 2024, the best market positions had long been taken by Xilinx.
A step behind means falling further behind.
V. There Is Only One Winner, But Not Because the Route Was Wrong
Reviewing the past decade, a core question arises: Was Intel's choice of the FPGA route a wrong judgment?
Not entirely, but the subtlety of the route lies in the timing.
The reason NVIDIA's GPU won is not because it is "technically better than FPGAs," but because the core of the AI computing power race is training, not inference. Training a large model requires absolute massive parallel computing power. In this regard, GPUs have a natural advantage—thousands of cores running matrix multiplication simultaneously; neither FPGAs nor ASICs can achieve this level of flexibility.
And after 2018, the "large model arms race" sparked by OpenAI, Google, and others caused the demand for training computing power to grow exponentially, making the GPU the only solution. NVIDIA's CUDA ecosystem has been accumulated for over a decade, with 5 million developers and native support for all mainstream frameworks—this is not something any FPGA vendor can catch up with in three to five years.
But this is not the whole story.
The other half of the reason for Intel's failure is the collapse of execution. Choosing the same FPGA route, AMD opened up new growth space in scenarios such as embedded AI, edge computing, and industrial control through the integration of Xilinx. AMD's data center business revenue in Q1 of fiscal year 2026 grew by 57% year-on-year, largely due to the combination of FPGA+CPU+GPU.
And Intel? Its CPU business is being eroded by AMD, its foundry business has been losing money year after year, its GPUs cannot catch up with NVIDIA, and it has lost its FPGA business. It wants to do everything, but fails to do anything well.
In December 2024, the Intel board finally took action. CEO Pat Gelsinger was dismissed. The first move after Lip-Bu Tan took over was to cut non-core assets—Altera was put on the block.
VI. Does FPGA Still Have a Chance?
But if you think the story of FPGA ends here, you might be missing the most interesting thing that is happening right now.
In March 2026, at the NVIDIA GTC conference, Jensen Huang released the next-generation AI computing platform, Vera Rubin. In the design of this platform, there is a detail worth pondering—
For the first time, FPGAs are listed as standard co-processing units for AI inference racks.
The Groq 3 LPX inference rack is equipped with 32 FPGAs per rack, with a unit price of about $12,000. What tasks do FPGAs undertake? Node interconnect scheduling, protocol conversion, and acceleration of preprocessing and postprocessing for inference tasks. GPUs are responsible for large-scale parallel computing, while FPGAs are responsible for flexible scheduling and low-latency control.
This is a landmark event—the FPGAs that were once crushed by GPUs have now been personally invited back to the table by Jensen Huang.
Why? Because the focus of AI computing power is shifting from training to inference.
Deloitte's data shows that in 2023, AI training loads accounted for about 60% of total computing power. By 2026, the proportion of inference loads has surged to 67%. Training a GPT only needs to be done once, but inference—every user conversation, every image generation, every code completion—has to be run countless times.
What are the characteristics of inference? Fixed model architecture, extreme cost sensitivity, and the need for low latency. These three characteristics are all within the comfort zone of FPGAs.
- Fixed model → No need for the general flexibility of GPUs; FPGAs can be deeply optimized for specific models
- Cost sensitivity → The energy efficiency ratio of FPGAs is much higher than that of GPUs, and large-scale deployment can save huge electricity bills
- Low latency → Direct hardware acceleration by FPGAs can reduce end-to-end latency by 30%-50%
Midjourney once published a piece of data: after migrating inference workloads from NVIDIA GPUs to Google TPUs, the monthly computing power cost dropped from $2.1 million to $700,000, a cut of 65%. This is the paradigm-shifting impact of dedicated chips on general-purpose GPUs.
And the positioning of FPGAs fits exactly in the gap between GPUs and ASICs: GPUs are too expensive and power-hungry, while ASICs are too rigid to adapt to algorithm iterations. FPGAs are programmable, reconfigurable, low-latency, and highly energy-efficient—perfectly filling this gap.
The data also speaks for itself. Frost & Sullivan predicts that in 2026, the global demand for FPGAs in AI servers will exceed 3.5 million units, with the FPGA usage per AI server reaching 3-5 times that of traditional servers. The lead time for high-end FPGAs has surged from 8-10 weeks to up to 52 weeks. Xilinx and Lattice successively announced price increases of 10%-20% in March 2026.
The shortage of NVIDIA GPUs is spilling over into the FPGA market. And when NVIDIA itself starts writing FPGAs into its reference designs, this trend is no longer a guess, but a fact that is happening right now.
Looking back at the ten years since Intel acquired Altera, we can draw a simple business lesson:
Choosing the right track is important, but how you run on that track is even more important.
The FPGA route chosen by Intel was not wrong in itself. AMD has proven through Xilinx that FPGAs have great potential in the AI era. But Intel's problem lies in: buying the best assets but lacking the ability to use them well. Insufficient internal priority, mismatched toolchains, process nodes dragging down product iteration, and the ecosystem puzzle breaking apart piece by piece—no matter how good the strategy is, without execution to support it, it is just castles in the air.
And what's next for Altera? After breaking away from Intel and receiving investment from Silver Lake Partners, the new CEO Raghib Hussain has already declared: to become the "world's number one FPGA solution provider." Altera's Agilex 5 series, with built-in AI Tensor Blocks, is targeting edge inference for industrial vision and medical devices, building its own differentiated advantages.
The story of FPGA is far from over. Under the triple trend of the continuously rising proportion of AI inference, the severe shortage of NVIDIA GPUs, and the explosion of demand for customized computing power, FPGAs may be looking forward to moving from a marginal role to the core table of data centers.