As AI moves from the cloud down to smart glasses, robots, and every terminal device, edge devices require real-time perception, real-time decision-making, and real-time execution. The test for chips is no longer just peak computing power, but a comprehensive capability encompassing power consumption, latency, interfaces, and scenario adaptation.
On September 10, at the "Edge AI Chip Power - 2026 Smart Terminal Chip Ecosystem Summit" co-hosted by Xinshiye and the IICIE (International IC & Innovation Exhibition), Zhang Weiping, Marketing Director of Hercules Micro, delivered a keynote speech titled "Hercules Micro FPGA & HPU: Empowering Intelligent Development Across Multiple Industries". Centering on the four major market waves of consumer electronics, machine vision, artificial intelligence, and industrial intelligence, he systematically elaborated on the company's strategic positioning, three-stage product roadmap, and heterogeneous computing layout for edge intelligence.
Of particular note, although Hercules Micro started with FPGA and has been deeply engaged in this field for many years, the company's current strategic direction is no longer confined to "single FPGA devices." The importance of the Heterogeneous Programmable Unit (HPU) is becoming increasingly prominent. The "FPGA & HPU" in the title of this speech is precisely a footnote to this strategic upgrade: FPGA provides the underlying capability of programmable logic, while HPU is a more complete computing form that integrates FPGA programmable logic with heterogeneous units such as CPU/MCU, NPU/DSP, security cores, and even communication and driver modules—it is no longer just a "glue logic device," but an integrated programmable computing platform for edge intelligence.
"Our company mainly focuses on FPGA, which is essentially a field-programmable logic array used to assist various existing applications—when there is no ready-made solution available, we provide one." With these opening remarks, Zhang Weiping introduced the logical starting point of Hercules Micro's expansion from FPGA to HPU.
01. Convergence of Four Major Waves: Comprehensive Explosion of Edge Computing Power Demand, Hercules Micro "Assists" Application Iteration
Zhang Weiping first started from the market perspective, outlining four converging and growing industrial waves: the global consumer electronics market is expected to reach USD 762.6 billion by 2026, with a CAGR of about 5.9%; the global machine vision market will exceed USD 28.6 billion by 2026, with a CAGR of 12.7%, and the Chinese market growth rate is as high as 16.3%; the global AI market is expected to exceed USD 222 billion by 2030; the global industrial intelligence market will exceed USD 486 billion by 2026, with the Chinese market becoming the core driving force with a growth rate of 19.7%. These four waves together constitute a broad stage for edge intelligent chips.
Under these waves, edge systems face common challenges. Zhang Weiping pointed out that whether it is robots, industrial cameras, or smart terminals, although main control chips have considered many scenarios during the design phase, the iteration of application scenarios is simply too fast, and the original solutions often "cannot keep up," still requiring flexible external access and supplementation. "Our products are to make up for everyone's application scenarios and make product iterations faster." Facing the dominant position of main control chips such as GPUs and CPUs, he gave a clear definition of the role of Hercules Micro's chip products: not a replacer, but an assisting partner. "We act as an assisting partner to them, rather than replacing them. We follow them to jointly adapt to the changes and iterations of this industry."
This idea was foreshadowed at the very beginning of its establishment. Zhang Weiping introduced that Hercules Micro is one of the earliest domestic manufacturers to step into the R&D of the "SoC + FPGA" heterogeneous architecture, and took the lead in implementing the FPGA + MCU heterogeneous solution, which can quickly hand over various data to the subsequent "brain" for processing after simple front-end processing at the edge.
02. CVI+ Strategy: Three-Stage Heterogeneous Evolution from FPGA to HPU
Starting with consumer electronics (C - Consumer), and focusing on "Vision for the Future (V - Vision)" and "Intelligent Services for Industry (I - Industry)", Hercules Micro takes the "CVI + three-stage development" as the strategic main line, planning a three-stage path of "1.0 Exploratory Entry → 2.0 Focusing on Vision and Edge Intelligence → 3.0 Embracing Industry and Intelligence."
In Stage 1.0, the M5 (FPGA + 8051 SoC) and M7 (FPGA + Cortex-M3 SoC) were launched in the industrial market, while self-developed chips such as H1D03, H3, and H3p were introduced in the consumer electronics market, quickly entering mass production at the client side with low cost and high adaptability.
In Stage 2.0, the company capitalized on the trend to launch the H7, P2, P3, and PV series to enter the vision field, among which the PV series is specifically designed for edge computing systems.
Stage 3.0 is a crucial step in strategic leap and a complete presentation of the HPU concept: facing emerging markets such as new energy, intelligent manufacturing, humanoid robots, smart healthcare, and automotive electric drive, it integrates heterogeneous units such as CPU/MCU, DSP/NPU, security cores, and FPGA into one, aiming to meet the extreme requirements of the edge market for performance, real-time capability, high reliability, and area with a single chip.
From the product roadmap, H7, P2, etc., have achieved mass production, PV65 has also begun mass production, and PV180 (180K LC) and H10 will be launched successively. Their common logic is to make data transmission to back-end processing units faster, better, and easier—this is precisely the core of moving from FPGA to HPU.
03. PV Pegasus Vision Series: Pioneer Sample of HPU Concept, Comprehensive Penetration in Six Major Scenarios
As a key promoted product line, the PV (Pegasus Vision) series is a pioneer sample of the HPU concept put into practice, integrating FPGA programmable logic and on-chip MCU in a single chip. It adopts a 6-input look-up table architecture, providing 40,800 LUT6s and 112 36Kb EMBs, built-in 104 DSPs, ARM Cortex-M3 MCU (200MHz), 32KB SRAM, and AES encryption, reaching the AEC-Q100 Grade 2 automotive grade; in terms of interfaces, SerDes supports 4 to 12.5Gbps and integrates hard-core PCIe Gen 3, MIPI C/D PHY reaches the industry-leading level (D-PHY 4.5Gbps, C-PHY 2.5Gsps), and it is also equipped with a hard-core DDR controller and LVDS high-speed IO, providing three capacity tiers of 65K, 35K, and 180K.
Relying on the FPGA + MCU synergy and a complete SDK, the PV series demonstrates its capabilities in six major scenarios: medical imaging (CT/MRI acceleration, real-time latency <1ms), intelligent video analysis (concurrent 16-channel 4K on a single platform), automotive electronics (multi-sensor fusion, AEC-Q100 G2 automotive grade), industrial quality inspection (processing speed >1000fps, zero missed detections), display backlighting (Mini-LED with 1000+ zones), and 8K video bridging (bandwidth 12.5Gbps). The six major scenarios span the two main lines of visual perception and intelligent industry, which exactly correspond to the two main pillars of V and I in the "CVI + three-stage strategy."
04. Ecosystem Advancement and Future: Completing NVIDIA's "Data Entry", H10 Steps Towards Mature HPU Form
A noteworthy detail in the speech is the synergy between Hercules Micro and NVIDIA's edge AI ecosystem. Addressing the pain points of complex sensor protocols and high integration costs, NVIDIA launched the Holoscan Sensor Bridge (HSB), which streams high-speed sensor data to GPU memory with zero-copy through FPGA hardware interfaces. The PV series is the ideal "front end" for HSB: by leveraging FPGA to flexibly expand the front end, data is directly sent into its processing environment according to NVIDIA's own standards through eleven 10-Gigabit Ethernet channels, completing the "sensor data input bottleneck" of NVIDIA's edge AI and forming a physical AI closed loop of Sensor → HSB → GPU → Simulation → Cloud.
The H10 platform previewed in this speech represents the mature form of HPU. "This CPU is not here to replace the subsequent processing or inference, but to help everyone process the data as quickly as possible at the edge layer, making the back-end load simpler," Zhang Weiping used this to point out the division of labor philosophy of HPU: heterogeneous units perform their respective duties and accelerate collaboratively. H10 adopts a dual-core AMP/SMP architecture, featuring microsecond-level real-time response, 4 to 10 TOPS heterogeneous computing power, and programmable flexibility, and meets ASIL-B/D and ISO 21434/26262 compliance requirements; it integrates controllers, AI acceleration, security modules, communication gateways, motion drives, and visual perception into a single chip, which traditionally requires 3 to 5 chips to achieve, fully supporting scenarios such as automotive ADAS, industrial vision, intelligent robots, and new energy.
When the iteration speed of edge AI is so fast that fixed-architecture main control chips "cannot keep up," a programmable, reconfigurable, and heterogeneously integrated computing base becomes the most flexible link connecting sensors and intelligent centers. Starting from FPGA, Hercules Micro is advancing its products from a single programmable logic device to an HPU heterogeneous programmable computing chip along the "CVI + three-stage development path"—serving mature scenarios such as medical imaging, industrial quality inspection, and automotive electronics, while also opening new entry points for embodied intelligence and autonomous driving by adapting to NVIDIA's HSB.
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This article is edited based on the guest's speech without changing the original meaning. If you have any questions, please contact WeChat: xsychief.