Author: Feng Ning
Over the past two years, the spotlight on chip shortages has been focused on GPUs and ASICs, while FPGAs remained relatively low-profile. However, this summer of 2026, news of FPGA shortages suddenly emerged—supply-side contraction signals are now spreading from AI computing chips to programmable logic chips.
01. FPGAs Face a Supply Storm
As early as March this year, global leading companies successively issued price hike notices covering their full range of flagship products, with increases concentrated between 10% and 20%. The new prices officially took effect starting in March 2026.
Among them, Lattice Semiconductor increased prices by 10% for its core products such as the MachXO and ECP5 series, covering mainstream application scenarios including industrial control, communication equipment, and consumer electronics.
The global FPGA market currently exhibits extremely high concentration, with the two companies mentioned earlier and Altera collectively monopolizing over 90% of the high-end FPGA market share.
Recently, a senior chip distributor stated, "Currently, there is an acute shortage of spot inventory for various overseas FPGA products, and spot prices have generally surged significantly. For example, the spot price for a single imported FPGA with an XC prefix model has risen from 220 RMB at the beginning of the year to 850 RMB. A single imported FPGA with an EP prefix model has increased from 120 RMB to 1,200 RMB, which is the latest data. Both are highly popular models in the European and American markets, and their spot prices have increased 7 to 10 times, which downstream domestic factories have accepted. If sourcing directly from the original manufacturers, the prices would not be this high, but a 52-week lead time is unavoidable. Imported FPGAs generally require this lead time now, and low-end models might take even longer."
52 weeks * 7 days = 364 days, a full year.
For a typical electronic manufacturing enterprise, this means forced extensions of product R&D cycles, delayed time-to-market, and missed market windows. So, what force has pushed an industrial standard component originally costing hundreds of RMB to the thousand-RMB level in less than a year?
02. Why Has the "Universal Chip" Suddenly Become "Hard to Find"?
The most core advantage of an FPGA is its programmable architecture, allowing designers to quickly program and repeatedly reconfigure the chip to implement various custom functions. Relying on online software downloads and updates, even if the FPGA is already soldered and integrated into the finished equipment, it can still be reprogrammed, which is the origin of the "field-programmable" in the name "Field-Programmable Gate Array." Leveraging this inherent flexibility, FPGA function development and modification can proceed synchronously with the overall system design, effectively shortening the product R&D cycle and accelerating the time-to-market of design solutions.
Parallel data processing is another prominent advantage of FPGAs. FPGAs contain massive logic gate circuits internally, naturally supporting parallel computing and executing multiple computing tasks simultaneously, which differs from the serial computing mode that executes instructions sequentially. This characteristic is highly suitable for high-performance computing scenarios such as AI (Artificial Intelligence), delivering stronger computing performance at lower clock frequencies and power consumption levels.
In contrast, common ICs (Integrated Circuits) such as MCUs (Microcontroller Units), MPUs (Microprocessor Units), ASICs (Application-Specific Integrated Circuits), and ASSPs (Application-Specific Standard Products) have fixed and unchangeable functions after mass production and deployment, and their operating modes are generally serial computing. On the one hand, the non-programmable characteristic significantly compresses the iteration space after equipment deployment, shortening the service life cycle of the whole machine. On the other hand, to handle large computing loads with serial processing, the clock frequency must be continuously increased, directly leading to a surge in power consumption. Scenarios like edge AI in networks require both powerful computing power and strict power consumption limits. The shortcomings of these traditional ICs are significantly amplified in such scenarios, making it difficult to meet usage requirements.
The supply-side gap acts as the "push," while the structural shift on the demand side serves as the "pull." The two forces are combining.
From the demand side, according to the latest report released by MarketsandMarkets, the global FPGA market is expected to see significant growth, increasing from $11.73 billion in 2025 to $19.34 billion in 2030. AI computing power and data centers are the core engines driving this round of growth.
In the field of AI computing power, a noteworthy structural shift is occurring: inference is replacing training as the main consumer of computing power. Data shows that in 2026, global inference computing power accounts for 70%-80% of the total AI computing load. This shift means that the market's evaluation criteria for computing chips are moving from simply pursuing peak computing performance (FLOPS) to focusing more on the comprehensive performance of latency, energy efficiency ratio, and Total Cost of Ownership (TCO).
Under this new evaluation system, the advantages of FPGAs are fully unleashed. Taking latency as an example, GPUs need to continuously allocate threads and schedule tasks when processing inference requests, generating additional uncertainty. In contrast, FPGAs map algorithms directly into hardware circuits, with data flowing through fixed physical paths, making response times highly predictable. In terms of power consumption, FPGAs typically consume far less power than GPUs of equivalent performance in large model edge inference. In latency-sensitive scenarios such as industrial control, autonomous driving, and real-time voice, the advantages of FPGAs are particularly evident.
In the data center field, the role of FPGAs is also upgrading—from hardware acceleration cards for specific algorithms to the interconnection and scheduling of entire computing clusters. In 2026, multiple AI servers have widely adopted a three-tier heterogeneous architecture of "CPU + GPU + FPGA": the CPU handles system management, the GPU focuses on large-scale parallel computing, and the FPGA takes on the coordination of data flow between multiple GPUs, as well as the offload preprocessing of network data packets. The core reason FPGAs are competent for this role remains their "reconfigurability." There are various high-speed interconnection protocols within data centers, and equipment from different manufacturers often speak different "languages." FPGAs can change protocol parsing logic at any time through online upgrades, adapting to new standards without replacing hardware.
On the supply side, overseas giants are strategically "sacrificing pawns to save the rooks." It is reported that as early as 2025, Xilinx shifted 70%-80% of its advanced capacity to high-margin AI-specific FPGAs, reducing the supply of mid-to-low-end products. After Intel (Altera) began independent operations, it also focused resources on data centers and the automotive sector, further tightening the capacity for general-purpose FPGAs. This strategy of "giants controlling production and tilting advanced capacity to the high end" has led to a continuous expansion of the supply gap in the mid-to-low-end market, resulting in a severe lack of overall supply elasticity for global FPGAs.
In this capacity reallocation, the most severely affected areas are general industrial control, communication base stations, and traditional embedded application fields. For example, communication equipment manufacturers face the risk of FPGA supply interruptions for 5G base stations, industrial automation enterprises are forced to delay the production scheduling of PLC and servo drive products, and automotive OEMs are experiencing "shortage anxiety" over core chips for autonomous driving domain controllers.
Against the backdrop of shrinking global FPGA supply, the reactive activation of "Plan B" by downstream manufacturers will significantly accelerate the introduction process of domestic chips.
03. Domestic FPGAs: The Opportunity Has Arrived
Process technology is the standard for distinguishing different generations of FPGAs and the primary metric to consider when evaluating them. As a type of digital chip, FPGAs inherently follow Moore's Law, with new generations of products launched every 2-3 years on average. Adopting more advanced process nodes can reduce power consumption, shrink chip size, and lower per-unit costs, making the performance of new-generation FPGAs generally superior to the previous generation. Therefore, the process node must be considered first when evaluating an FPGA. For example, Xilinx's "Versal" product utilizes TSMC's (Taiwan Semiconductor Manufacturing Company) 7nm FinFET process. Altera's Agilex 3 series FPGAs are based on Intel's 7nm process.
The number of logic elements in an FPGA represents its basic logic capacity or scale. A logic element is the basic unit for an FPGA to implement programmable functions, typically containing a Look-Up Table (LUT) and a register. The LUT implements combinational logic, and the register implements sequential logic; the combination enables a logic element to implement basic digital circuit functions. Therefore, the more logic elements there are, the larger and more complex the circuit scale the FPGA chip can accommodate and implement, making it one of the key metrics for evaluating FPGA chip capabilities. For example, the VP1902 (Versal Premium) launched by AMD in June 2023 has up to 18.5 million logic elements. Intel's Stratix 10 GX 10M FPGA has 10.2 million logic elements and integrates 43.3 billion transistors.
The main domestic FPGA players are Fudan Microelectronics, Anlogic, and Pango Microsystems. Given that the current shortage mainly involves general-purpose products, and domestic manufacturers have already gained considerable competitiveness in process nodes and performance, they can effectively meet this portion of the demand.
Fudan Microelectronics has launched four major series of products, namely: ten-million-gate-level FPGA chips, hundred-million-gate-level FPGA chips, billion-gate-level FPGA chips, and Programmable System-on-Chip (PSoC) embedded programmable devices, covering high-reliability fields such as communications, industrial control, and automotive electronics. Among them, the 28nm process hundred-million-gate-level FPGAs and PSoC chips serve as the flagship products.
Building on this, the company has developed ultra-large-scale FPGA products based on the 1xnm FinFET advanced process and adopted fan-out and 2.5D advanced packaging to increase chip capacity. Its FPGA chip products feature logic resources ranging from 50K to 4000K, and the high-speed serial interface rate can reach up to 32Gbps. The company is the pioneer of the RF-FPGA monolithic architecture, with RFADC sampling rates reaching 5Gbps.
The process technology and SerDes (high-speed serial interface) rate of FPGAs directly determine the product's bargaining power in the high-end market. Previously, Xilinx and Altera occupied over 90% of the high-end market share relying on their 7nm/10nm process nodes and 112G SerDes rates.
After more than a decade of accumulation, Pango Microsystems has built a complete product matrix covering 28nm-40nm, comprising eight major product families: Compa, Logos, Logos-2, Titan-2, Titan-3, Kosmo-2, Kosmo-3, and Visto-3.
Among them, the Compa series consists of CPLD products essential for board-level management control and IO expansion. In addition to achieving high-volume shipments in traditional communication and industrial fields, it has also completed product introduction and mass production with key customers in data center servers. The Logos series provides customers with ultimate cost-effectiveness. The Titan series is positioned as high-performance FPGAs. The Titan-3 series, based on advanced FinFET process, features a maximum scale of up to 1300K logic elements, making it the most high-end domestically owned and produced FPGA product currently mass-produced in China. Among them, PG3T1300 and PG3T1500 are the only two hundred-million-gate-level high-end domestically owned FPGA products in China, and have become the main domestic products in scenarios such as high-end communications, network security, high-end industry, and data centers. The Kosmo-2/3 series adopts a "CPU + FPGA + NPU" multi-core heterogeneous architecture, providing customers with highly competitive and highly integrated system-level solutions to help customers in industrial control, video imaging, communications, and AI fields succeed. The Visto-3 series, currently under development, targets ultra-large-scale high-end scenarios, aiming to fill the domestic gaps in key fields such as new-generation communication technologies, data centers, semiconductor equipment, SoC (System on Chip) prototyping verification, and EDA simulation accelerators.
Anlogic has achieved coverage of key models for 55nm, 28nm, and FinFET process node FPGA chips, with cumulative product shipments exceeding 200 million units. The company's FPGA chips based on the domestic 28nm process have achieved mass production and delivery, and high-performance FPGA chips based on advanced processes (FinFET) have also been mass-produced and delivered. In 2026, Anlogic launched the fifth-generation low-power EF5 series and the mid-to-high-end PH1P series new products, further enriching its general-purpose product line. Among them, the automotive-grade version of the PH1P series has passed the AEC-Q100 Grade 2 certification and obtained mass production validation from leading automakers, indicating that its maturity and reliability have been recognized by the market.
In addition, Gowin Semiconductor's Arora and LittleBee series, Efinix's Titanium series, etc., all have mature layouts in the low-to-medium density general-purpose market. Although these products do not match the absolute performance of Xilinx's high-end Versal series, they possess the corresponding support capabilities to address the current shortage areas in industrial control, communication interfaces, and consumer electronics.
More crucially, it is the delivery capability. The current 52-week lead time for imported FPGAs stems from the tilt in overseas capacity and supply chain disruptions, whereas domestic FPGAs mostly adopt domestic or controllable foundry production lines, resulting in relatively stable capacity scheduling. For downstream complete machine manufacturers eager to recapture market windows, shortening the waiting time by half a year is itself of immense commercial value. Once downstream manufacturers complete the hardware design and software adaptation for domestic solutions, the switching costs will be significantly reduced, forming strong customer stickiness. This means that customers introduced during the current shortage window period can potentially be transformed into long-term partners, establishing a continuous market base for domestic manufacturers.