On September 20, 2026, the 11th Shanghai FD-SOI Forum was held in Shanghai as scheduled. Hosted by VeriSilicon, the event gathered core enterprises from the global semiconductor supply chain, including GlobalFoundries, Soitec, SimWings, and MIPS, as well as top industry research and academic teams such as IBS, Tsinghua University, and the National University of Singapore, sharing the latest progress in FD-SOI (Fully Depleted Silicon-on-Insulator) technology.
In his opening address, Wayne Dai, Chairman, CEO, and President of VeriSilicon, disclosed the technical foundation, industrial milestones, and the latest progress of FD-SOI's localization in China. Handel Jones, CEO of International Business Strategies (IBS), systematically elaborated on how Artificial Intelligence (AI) is reshaping the global semiconductor industry landscape and deeply analyzed the key role of FD-SOI technology in this transformation.
Driven by AI, the Global Semiconductor Market Will Exceed USD 4.6 Trillion by 2035
Jones first presented IBS's long-term forecast for the semiconductor market. Data shows that the global semiconductor market will grow from USD 446.7 billion in 2020 to USD 1.586 trillion in 2026, reach USD 2.585 trillion in 2030, and further climb to approximately USD 4.678 trillion in 2035. The primary drivers of this growth are the rapid development of generative AI and agentic AI.
"Generative AI has led to a substantial increase in data center capital expenditures, particularly driven by the surging demand for NVIDIA GPUs," Jones stated. "Meanwhile, agentic AI further pushes up data center capital expenditures, which are projected to reach USD 1.1 trillion in 2026 and maintain a similar level in 2027." He specifically mentioned that the widespread use of agentic AI applications like Claude requires a massive amount of inference tokens, directly driving the demand for high-performance computing chips.
IBS data indicates explosive growth in the daily consumption of AI tokens in the US and China. By the first quarter of 2030, China's daily AI token consumption is expected to reach 3,500 trillion, while the US will reach 2,250 trillion.
Jones emphasized, "To generate such a massive volume of tokens, the cost per token must be significantly reduced. NVIDIA is achieving this goal through next-generation systems, lowering the cost from USD 4.20 per million tokens in the Hopper system to USD 0.12 in the Blackwell system, and further to USD 0.01 in the Rubin system."
Surge in Data Center Capital Expenditures: Opportunities and Challenges Coexist
Jones also provided a detailed analysis of the data center capital expenditure trends of major global tech companies. The capital expenditures for giants like Amazon, Alphabet, Microsoft, and Meta in 2026 are projected to reach USD 220 billion, USD 200 billion, USD 175 billion, and USD 137.5 billion respectively, driving the total data center capital expenditure to USD 1.1 trillion, a year-on-year increase of 92.5%.
However, Jones also warned that this ambitious spending plan faces significant challenges. "The main challenge lies in whether sufficient semiconductor and power supplies can be secured," he pointed out. He noted that shortages in wafer and packaging capacity are affecting the supply chain, and the supply-demand ratios for many products indicate that the tight supply of advanced process chips (such as logic chips and accelerators ≤2nm) will persist until 2028.
Strong Growth in DRAM and NAND Markets, Yet Hidden Concerns Remain
Regarding the memory market, Jones predicted that the DRAM market will reach USD 1.08 trillion in 2030 and further grow to USD 1.84 trillion in 2035. The high growth in the DRAM market mainly stems from the AI-driven increase in the average unit price per GB and the growth in shipment volume (expected to increase by about 18% in 2026).
DRAM manufacturers are significantly increasing their capital expenditures in 2026 and 2027 (Micron's 2026 capital expenditure is USD 32.6 billion, a year-on-year increase of 114.8%; SK Hynix is USD 31 billion, a year-on-year increase of 100%). Meanwhile, DRAM technology is migrating to the 4F2 structure, a vertical channel transistor structure that can achieve higher storage density within the same area. The combined result is that DRAM capacity expansion will outpace demand growth, potentially leading to oversupply.
IBS also pointed out three technological trends that reduce DRAM demand:
1. New algorithms reduce DRAM demand and increase SRAM usage: In inference scenarios, algorithm optimization can reduce reliance on DRAM capacity, shifting towards increased SRAM usage. SRAM is faster and consumes less power, but is more expensive and has smaller capacity. If this trend continues, it will weaken DRAM demand in the inference market.
2. NAND-assisted decoding becomes a new architecture: Utilizing NAND flash memory to support the decoding tasks of processors is a new architectural approach. NAND costs less than DRAM; if it can replace DRAM functions in some scenarios, it will further compress DRAM demand.
3. Inference market shifts from HBM to LPDDR5X/LPDDR6: This is the most critical structural change. Although HBM has extremely high bandwidth, it is expensive—every 1GB of discrete DRAM requires 3GB of DRAM to support HBM. LPDDR5X and LPDDR6 offer better cost-effectiveness in inference scenarios. If inference becomes the main workload for AI computing, the demand structure for DRAM will shift from HBM to LPDDR, and the DRAM usage per unit of computing power may decline.
IBS warned of two macroeconomic risks facing the DRAM market:
1. A global recession may occur in the second half of 2027 or the first half of 2028, which will weaken consumer spending and subsequently affect the demand for DRAM in consumer electronics (PCs, smartphones, TVs, etc.).
"The DRAM shortage has already negatively impacted shipments in multiple application sectors in 2026," Jones cited data to point out that PC shipments will drop by 19.4% in 2026, smartphones by 22.6%, TVs by 17.3%, and automobiles by 5.0%.
2. The probability of data center capital expenditures declining in 2028 is increasing. Data centers are the core engine for current DRAM demand growth; if capital expenditures slow down, the DRAM market will lose its most crucial growth driver.
IBS's final judgment on the DRAM market is as follows:
Long-term (up to 2030): The DRAM market will maintain strong growth as AI inference requires more tokens. Token generation requires massive memory bandwidth and capacity, which is the fundamental support for DRAM demand.
Short-term risks: Overheated capital expenditures, capacity expansion brought by the 4F2 migration, algorithm and architecture optimization reducing DRAM demand, global recession risks, and potential declines in data center capital expenditures—these factors may form adjustment pressures in 2027-2028.
Outstanding performance of CXMT: IBS specifically named CXMT, believing its performance is "outstanding".
Regarding the NAND market, IBS believes that the NAND shortage may persist, but the Compute NAND (SLC and MLC) and Storage NAND (TLC and QLC) markets will diverge.
The core drivers of the NAND shortage are twofold:
1. Explosion in data center demand: The demand for Enterprise SSDs from AI inference systems and hyperscale data centers is growing geometrically. Additionally, traditional HDDs continue to face structural shortages, prompting a large number of orders to shift to QLC Enterprise SSDs.
2. High price per GB: NAND contract prices saw a quarter-on-quarter increase of over 55% in the first quarter of 2026, and are expected to rise further by 70% to 75% in the second quarter. The price of consumer-grade 1TB SSDs has almost doubled from about USD 45 at the end of 2025.
IBS also highly praised China's major NAND manufacturer, YMTC. YMTC's revenue reached USD 6.7 billion in the first quarter of 2026, and is expected to be about USD 11.5 billion in the second quarter. "YMTC's logic chip design under the NAND memory stack is highly innovative, and its IPO valuation is expected to be very high."
Agentic AI Smartphones and Physical AI: New Growth Engines
Jones views agentic AI smartphones as a new growth point in the smartphone market. He predicts that shipments of agentic AI smartphones will surge from 15.5 million units in 2026 to 1.33 billion units in 2035, accounting for nearly 50% of total smartphone shipments. These phones will require 150-200 TOPS of NPU computing power, adopt the 1.4nm or 2nm process, and be paired with LPDDR6 or LPDDR7 memory.
In the field of physical AI, Jones specifically emphasized China's leadership in robotics. He predicted that by 2035, global humanoid robot production will reach 11.78 million units, with China accounting for about 75%. "Chinese companies have a leading advantage in robotics technology, which will bring huge opportunities for semiconductor technologies such as FD-SOI."
The smart glasses market is also regarded by Jones as an important growth point. He predicted that the semiconductor market for smart glasses will grow from USD 1.607 billion in 2025 to USD 59.645 billion in 2035, with China's market share increasing from 19% to 48%.
Wafer Foundry Market: Intensified Competition in Advanced Processes
In the wafer foundry market, Jones predicted that the market size will reach USD 1.037 trillion by 2035, of which the market value of the ≤2nm process will reach USD 177.4 billion in 2030. TSMC will hold a 90% share of the advanced foundry market in 2030, with its ≤2nm wafer capacity reaching 300,000 to 350,000 wafers per month.
"Samsung's second-generation 2nm process is competitive with TSMC's 2nm in terms of PPA, and Intel's 18A is also being improved," Jones stated. "However, Intel's foundry capacity has been fully booked by internal demand."
Jones also pointed out that mature process capacity is currently oversupplied but will face shortages in the future, especially the 28nm process, which will be tight due to demand from imaging applications. He specifically mentioned, "The strong demand for GlobalFoundries' 22nm FD-SOI demonstrates the importance of specialty technology."
During the speech, Handel Jones also provided a detailed analysis of the capital expenditure (CAPEX) trends of major global semiconductor companies. IBS data shows that the total capital expenditure of major global semiconductor companies will grow from USD 163.27 billion in 2025 to USD 258.44 billion in 2026, an increase of up to 58.29%.
Looking at specific companies, TSMC's capital expenditure in 2026 is expected to be USD 62 billion, an increase of about 51.6% from USD 40.9 billion in 2025, continuing to rank first globally in semiconductor capital expenditure. Samsung Electronics is also expected to spend USD 62 billion, a substantial increase of 88.4% from USD 32.91 billion in 2025, demonstrating its strong intention to catch up with TSMC in memory and advanced processes.
Regarding memory manufacturers, Micron Technology's capital expenditure in 2026 is expected to be USD 32.6 billion, an increase of 114.8% from USD 15.18 billion in 2025; SK Hynix is expected to be USD 31 billion, an increase of 100% from USD 15.5 billion in 2025. The doubling of capital expenditures by both companies reflects the explosive growth in demand for HBM and high-end DRAM driven by AI.
For Chinese manufacturers, CXMT's capital expenditure in 2026 is expected to be USD 8.1 billion, an increase of 13.9% from USD 7.11 billion in 2025; YMTC is expected to be USD 7.5 billion, an increase of 44.8% from USD 5.18 billion in 2025. SMIC's capital expenditure in 2026 is expected to be USD 6.8 billion, a decrease of 16.0% from USD 8.1 billion in 2025, showing its cautious attitude towards mature process expansion.
Notably, Intel's capital expenditure in 2026 is expected to be USD 20 billion, an increase of 36.5% from USD 14.65 billion in 2025, but its foundry capacity has been fully booked by internal demand. In addition, the combined capital expenditure of "other" semiconductor companies is expected to be USD 35.24 billion, an increase of 10.6% from USD 31.86 billion in 2025.
Jones pointed out that the main drivers of this round of capital expenditure expansion come from AI data center construction, the advanced process race, and memory demand growth. However, he also warned that whether the high-speed growth of capital expenditures can be sustained depends on whether data center companies can secure sufficient semiconductor and power supplies, as well as the stability of the global macroeconomic environment. IBS predicts that after a substantial increase in 2026, the semiconductor industry's capital expenditure will remain at a high level in 2027 but may face adjustment pressures in 2028.
The continuous growth in foundry capital expenditure is highly beneficial for WFE (Wafer Fab Equipment) manufacturers. IBS expects that WFE expenditure will account for about 70% of the total foundry capital expenditure.
China's Semiconductor Industry: Continuously Enhancing Competitiveness
Jones highly praised the progress of China's semiconductor industry. The data he presented shows that Chinese companies' global competitiveness in multiple fields continues to improve. From 2020 to 2035, the global competitiveness scores for products such as converged processors, display drivers, SiC MOSFETs, NAND, and MCUs (Microcontroller Units) have significantly increased.
"Chinese semiconductor companies are continuously strengthening their supply capabilities in the Chinese market, their product portfolios are becoming highly competitive, and their design capabilities are also improving," Jones stated. "The critical need is to secure sufficient wafer capacity; many technological fields will face shortages in the future."
He specifically mentioned that CXMT and YMTC have shown very strong performance, VeriSilicon has numerous clients in China, and Huawei's LogicFolding technology is highly effective for Ascend processors and Kirin chips.
FD-SOI: A CMOS Continuation Scheme Sharing the Same Origin as FinFET
In Jones's view, the AI-driven growth of the semiconductor industry will also greatly promote the development of the FD-SOI ecosystem. In the Chinese market, where advanced process development is restricted, FD-SOI has even broader prospects.
In his opening address at the conference, Wayne Dai, Chairman, CEO, and President of VeriSilicon, traced the origin of FD-SOI technology: in 2001, the team led by Professor Chenming Hu at the University of California, Berkeley, first proposed two major technological directions to advance CMOS processes below the 20nm node, namely the 3D fully depleted FinFET and the 2D fully depleted FD-SOI. The two are not substitute relationships but complementary technology routes targeting different application scenarios.
In ordinary bulk silicon transistors, there is thick silicon below the current channel, which requires doping for isolation. SOI (Silicon-on-Insulator), on the other hand, has a three-layer structure: top silicon, buried oxide (BOX), and handle wafer. Among them, the "buried oxide" is the insulating layer, which cuts off the electrical connection between the top silicon and the handle wafer. This brings three major benefits: it eliminates parasitic capacitance, allowing current to flow faster; significantly reduces leakage current; and because of the insulating layer isolation, it is highly resistant to external interference and radiation.
As for FD-SOI, its top silicon is extremely thin (usually below 10nm), making it an SOI structure thin enough that the entire silicon layer is depleted (which is the origin of the name "fully depleted").
The core technical characteristics of FD-SOI can be summarized as follows:
1. Ultra-Thin Body: The extremely thin silicon film is the prerequisite for realizing the "fully depleted" physical mechanism. Together with the ultra-thin buried oxide layer, it forms the UTBB (Ultra-Thin Body and Buried Oxide) structure, which is key to advanced FD-SOI nodes.
2. Buried Oxide: The BOX layer provides full dielectric isolation. This structure fundamentally eliminates the parasitic thyristor paths in traditional bulk silicon CMOS, making the device naturally immune to latch-up effects.
3. Fully Depleted: Due to the extremely thin top silicon film, the channel region is completely depleted when the transistor is in the off state, eliminating the long-standing leakage current problem in traditional bulk silicon transistors.
4. No Channel Doping: Unlike traditional processes that rely on ion implantation to adjust the threshold voltage, the channel in FD-SOI is usually close to intrinsic (undoped), which significantly reduces Random Dopant Fluctuation (RDF) and improves device consistency.
In contrast, FinFET relies on a 3D fin structure and dominates scenarios pursuing ultimate computing power, such as cloud high-performance computing and flagship consumer electronics. Meanwhile, FD-SOI, with its inherent low power consumption, high integration, and strong analog-digital convergence capabilities, has become the optimal technology carrier for edge scenarios.
Dai Wei clearly pointed out that there is no either-or elimination relationship between the two technology routes of FD-SOI and FinFET; instead, they cover different core markets respectively, thus requiring a "two-legged" parallel approach.
FD-SOI Begins to Transition from 28nm to the 7nm Node
Looking at the key implementation nodes of the FD-SOI industry over the past decade, the global FD-SOI technology iteration has now entered an acceleration phase:
Specifically, in January 2025, the "FAMES Pilot Line" (based on FD-SOI technology), with a total EU budget of EUR 830 million, was officially launched in Brussels. It involves the joint participation of 11 industrial and academic institutions from 8 countries, aligning with the advanced process layout goals of the EU "Chips Act." In January 2026, the FAMES Pilot Line officially delivered the first 10nm FD-SOI path exploration PDK. In June 2026, the gate-level SADP lithography process for the 7nm FD-SOI node was realized, marking that the FD-SOI process is about to advance to the 7nm and below advanced nodes.
Currently, the FD-SOI process route has formed a complete iteration path from 28nm, 22nm, 18nm, and 12nm to 10nm, 7nm, and below, thoroughly breaking the industry's previous stereotypical perception that "FD-SOI is confined to mature nodes."
It should be pointed out that 28nm/22nm FD-SOI can match or even surpass the expensive 12nm/7nm FinFET (Fin Field-Effect Transistor) in terms of power consumption and performance, but at a lower cost. This also makes it possible to achieve better performance without the need for expensive advanced lithography equipment.
FD-SOI Market: To Reach USD 55 Billion by 2030
Jones also conducted an in-depth analysis of FD-SOI technology. Jones pointed out that FD-SOI has lower power consumption and better high-frequency performance compared to bulk silicon CMOS or FinFET. GlobalFoundries' 22nm FD-SOI (22FDX) has achieved mass production in 2025, proving the advantages of this technology.
"FD-SOI is highly effective for high-frequency applications, with a cutoff frequency potentially exceeding 500GHz and good linearity," Jones stated. "Adopting FD-SOI for Wi-Fi 7 and Wi-Fi 8 may result in lower power consumption compared to other technologies."
Tim Breen, CEO of GlobalFoundries, predicted that within the next decade, we will enter the era of Physical AI. The system requirements of Physical AI happen to structurally match the inherent advantages of GlobalFoundries' FD-SOI technology.
Currently, FD-SOI is in mass production at the 28nm process, in large-scale mass production at 22nm, and approaching mass production at 18nm. Jones predicted that by 2030, the total FD-SOI market size will reach USD 55 billion. In the future, at the 16nm and more advanced process nodes, adopting the FD-SOI process can achieve double-digit percentage cost reductions compared to other competing technologies; for example, at 5nm, costs can be reduced by up to 28%.
"FD-SOI may occupy a higher share of the wafer foundry market in 2030," Jones emphasized. "The next-generation FD-SOI has greater market potential than 22FDX, and STMicroelectronics' 18nm FD-SOI is expected to achieve growth."
IBS estimates that by 2030, in terms of market penetration, FD-SOI will have an extremely high penetration rate at mature nodes (22nm, 28nm) (88%–90%), and a lower penetration rate at advanced nodes (only 15% at the 5nm node). FD-SOI's share in the "combined market of the five nodes: 5nm/7nm/16-12nm/22nm/28nm" will reach 38.6%.
Broad Prospects for China's FD-SOI Market
Handel Jones also painted a magnificent picture of the semiconductor industry's development driven by AI for the attendees. From data centers to agentic AI smartphones, from humanoid robots to smart glasses, AI is creating unprecedented semiconductor demand. With its unique performance advantages, FD-SOI technology will play an important role in this wave, especially in China's booming physical AI ecosystem.
Jones specifically pointed out that FD-SOI has broad application prospects in China, especially suitable for physical AI applications. He listed application fields such as smart glasses, smartwatches, robots (over 8 million humanoid robots by 2035), and automotive electronics.
"It will be highly beneficial for Chinese companies to use FD-SOI for physical AI applications," Jones stated. "The low power consumption and high-frequency characteristics of FD-SOI make it an ideal choice for these applications."
Despite the optimistic prospects, Jones also warned of potential economic risks. He mentioned that US consumer debt is increasing, China continues to rely heavily on exports, and AI will reduce employment in many industries. "If a global recession occurs, it will impact the semiconductor market." He specifically pointed out that a global recession may occur in the second half of 2027 or the first half of 2028, and data center capital expenditures may decline in 2028.
However, Jones remains optimistic about the long-term prospects. "The semiconductor market will experience a downturn in the future, but it will achieve strong growth in the long run. The key factors are the timing and depth of the downturn phase."
Breakthroughs in China's Localization: 12-inch FD-SOI Production Line and Supply Chain Implementation
The most noteworthy Chinese local progress at this forum is that in August 2026, SOI Micro completed its Series B strategic financing led by institutions such as YMTC Capital and Optics Valley Venture Capital, and will build China's first large-scale mass production line for FD-SOI.
According to Dai Wei, SOI Micro was founded in 2022 and is the first domestic wafer manufacturing enterprise focusing on advanced FD-SOI processes. Coupled with NSIG acquiring a 14.5% stake in Soitec previously, and SimWings obtaining the Soitec Smart-Cut technology license, a complete local supply chain from 12-inch FD-SOI substrate supply to wafer manufacturing has been formed in China.
According to SimWings' 300mm SOI roadmap, its HVSOI, RF SOI, and Si-Ph SOI substrate products have been mass-produced in 2026, mainly covering power, RF, and silicon photonics fields. Meanwhile, FD-SOI dedicated substrates (which have extremely high requirements for substrate quality and long certification cycles) are in the pilot run stage in 2026 and are expected to achieve mass production in 2027.
Regarding the mass production progress of 300mm SOI wafers, Wang Kerui, Executive Deputy General Manager of SimWings, revealed four key pieces of information: first, the products are qualified, with BCD, RF, and silicon photonics products passing certification; second, clean and protected IP, with continuous cooperation with Soitec to extend the license from 200mm to 300mm; third, a secure SOI supply chain, especially for the Chinese market, where NSIG fully guarantees wafer supply internally to ensure 300mm SOI supply, and the products have been certified by customers; fourth, reliable 300mm SOI capacity, reaching 33K wafers per month by 2026, and capacity expansion of over 1 million pieces per year is already in planning.
The implementation of the domestic FD-SOI supply chain will directly support four high-potential core markets: automotive electronics, IoT and wearables, mobile communications, 5G/6G radar, and edge AI.
According to market data disclosed at the forum, the global monthly equivalent wafer demand for FD-SOI will continuously grow from about 716,000 pieces in 2026 to 1.276 million pieces in 2030. Segmented tracks such as MCUs, display drivers, and image sensors will maintain a stable double-digit compound annual growth rate.
The Future of FD-SOI
Tim Breen, CEO of GlobalFoundries, also looked forward to the future roadmap of FD-SOI technology at this forum and announced that "next-generation FDX innovations are coming." He pointed out four key development directions:
1. Advanced materials and devices: Achieving higher performance and lower power consumption through material and strain innovation;
2. Integrated AI memory: Embedded memory empowering edge AI and compute-in-memory;
3. Next-generation RF and quantum technologies: Bringing RF innovations for 5G/6G connectivity and emerging quantum systems;
4. 3D system integration: 3D heterogeneous integration, combining sensing, computing, and storage.
Tim Breen emphasized that as AI moves from the cloud to the physical world, the semiconductor industry is ushering in a new cycle of innovation. With its unique advantages in energy efficiency, RF performance, and integrated memory, FD-SOI technology will become the core underlying technology driving the development of physical AI.
Editor: Xinzhixun - Langkejian