This year's WAIC 2026 has been dominated by cloud-based AI high-computing-power chips. However, amidst the clamor for large chips, edge AI chips are also undergoing changes. Manufacturers are beginning to consider how to deploy more powerful AI capabilities to the edge. After two years of rapid development in large models, edge AI chip manufacturers have collectively "upgraded" overnight: 3D stacking, compute-in-memory (CIM), and counterattacking the cloud from the edge. These three trends intertwine on the exhibition floor of WAIC 2026 to paint a new industrial landscape, which may redefine the ultimate form of AI computing power.
01. SoC and Coprocessor: Two Forms of Edge AI Chips
Looking across WAIC 2026, the most intuitive feeling is that edge AI chips are splitting into two worlds.
On one side is the SoC (System on Chip) route. Zhixin Technology's P1 chip (CP8180) integrates a 12-core CPU, a 10-core GPU, and a 3-core self-developed NPU, with an overall computing power of 45 TOPS, compressing a complete "AI computer" into a single chip. The advantage of this "fully integrated" solution lies in its complete ecosystem: customers can directly run Linux or Android systems (and even Windows systems) without the need for an additional host controller chip. Rockchip's RK3588 is an old face at the edge. From tablets to automotive cockpits, and from TVs to robots, this general-purpose SoC equipped with a 6 TOPS NPU has penetrated thousands of industries in AIoT.
On the other side is the edge coprocessor, which is a more active track at this WAIC 2026. Including Guangyu Xinchen's TC1020 chip, Houmo AI's Manjie M50 chip, Rockchip's RK1828/1820 chips, Weiheng Technology's Fuguang LPU, and Xindongli Technology's RPP chip, none of them have the ability to independently run an operating system. Instead, they work as "AI add-ons" in coordination with the host controller chip through standard interfaces. "The coprocessor does not run the operating system, but accelerates AI inference. You can think of it as an NPU," explained a Rockchip engineer. "It needs to be paired with a host controller. The RK3588 + RK1828 is our golden combination." This "host controller + coprocessor" architecture allows users to smoothly upgrade computing power through interfaces such as PCIe without overthrowing the original system.
The physical forms of coprocessors are also becoming increasingly diverse. PCIe x16 slots (such as Houmo AI's Limou LM5070), PCIe x4 slots (such as Houmo AI's Limou LM5030), M.2 interface modules (such as Xindongli Technology's AzureBlade M.2 acceleration card), USB connections, and even SO-DIMM memory slot forms. On the Houmo AI booth, a dual-chip architecture acceleration card form (Houmo AI's Liqing LQ50 Due M.2 card) connected by two side-by-side M.2 interfaces was even exhibited. The two M50 chips mounted on it are interconnected via the C2C protocol. This idea of "stackable small computing power" is reshaping the hardware form of edge AI. Computing architectures are also blooming: Rockchip, Guangyu Xinchen, and Houmo AI are betting on NPUs; SOPHGO is deeply cultivating the TPU route; Xindongli Technology has chosen GPGPUs compatible with the CUDA ecosystem; and Weiheng Technology is laying out LPUs.
Behind the divergence of routes is the different trade-offs between "flexibility" and "computing power density" in edge scenarios. A Rockchip staff member frankly admitted, "The coprocessor and the host controller are decoupled. The customer's system has already been developed. If the computing power is insufficient, they can just plug in a coprocessor box without affecting the host controller's business."
02. 3D Stacking "Sinks": The Memory Wall for Edge Chips is Broken
At WAIC 2026 this year, not only are cloud chips massively betting on the 3D stacking technology route, but edge AI chips are also making great efforts. The technology of 3D stacking is sinking to the edge at an unexpected speed.
Rockchip's RK1828 claims to be "the industry's first mass-produced 3D stacked edge chip," with DRAM directly stacked on the NPU. The storage capacity is optional at 2.5GB or 5GB, and the theoretical bandwidth is about 1TB/s. In the on-site demonstration, a TV equipped with the RK1828 is converting ordinary video sources into 3D images in real time; the inference speed of the 3B large model exceeds 100 tokens/s, while the RK3588 running the same model only achieves a dozen tokens/s, an improvement of nearly an order of magnitude. A Rockchip engineer stated, "3D stacking has a huge impact on this. Large models require a massive amount of memory movement, which previous edge chips simply could not handle." Guangyu Xinchen globally launched the TC1000 series, the first edge high-computing-power 3D stacked near-memory computing low-power large model inference chip. Relying on its self-developed 3D stacked near-memory computing architecture + compute-in-memory technology + memory hierarchical technology, it achieves a 10-fold leap in equivalent bandwidth and only 1/3 of the power consumption of traditional solutions with the same computing power. Its hardcore performance breaks through the industry ceiling: it has achieved ultra-high-speed inference of 300 tokens/s for the 3B model on a single chip and supports high-performance operation of 35B-scale large models. The currently exhibited TC1020 chip has a computing power of 56 TOPS@INT8, 5/10GB storage capacity, a 7B LLM model decoding speed of >200 Tokens/s, and a product power consumption of only 8-15W. Although Weiheng Technology's products have not yet been taped out, it has planned the specifications for the Fuguang Englight-LPU chip, with a computing power reaching 256 TFLOPS. It adopts a 3D+2D heterogeneous memory architecture, in which the 3D stacked memory reaches 10~40GB with a bandwidth of 5 TB/s, and the 2D extended memory is 8~64GB with a bandwidth of 136 GB/s. A single chip supports 200B large models.
The reason why 3D stacking has exploded collectively in 2026 fundamentally lies in the fact that the bandwidth bottleneck of Transformer inference has been recognized by the industry. A technician from Guangyu Xinchen hit the nail on the head: "When Transformers perform inference, it is a bandwidth bottleneck, which has little to do with computing power. No matter how fast your computing core is, it is useless if the data cannot be moved over." However, 3D stacking is not without its costs. Built-in DRAM pushes up chip costs, and the capacity is still limited. 5GB is still inadequate for models above 35B. To this end, various companies have adopted "add-on" strategies: Guangyu Xinchen has reserved an LPDDR5 interface on the chip to expand external memory; Rockchip has planned multi-chip cascading functions on the next-generation coprocessor, and multiple chips connected together can break the 10-billion-parameter mark. A noteworthy industry consensus is forming: 35B parameters are the "sweet spot size" for edge Agents. A technician from Guangyu Xinchen explained, "Models below 35B are not good enough for Agents; their capabilities are insufficient. 35B is considered a reasonable size for running edge Agents nowadays."
03. Compute-in-Memory Steps Out of the Lab: SRAM, MRAM, and "True CIM"
If 3D stacking solves "moving fast," then compute-in-memory (CIM) pursues "no need to move." At WAIC 2026, compute-in-memory is no longer a concept, but a technology route that has been taped out and even mass-produced.
Houmo AI is the most radical practitioner in China. Its M50 chip has been mass-produced, using SRAM as the compute-in-memory core, embedding the computing units directly into the memory array. This is not simple near-memory computing (3D stacking belongs to this category), but circuit-level in-memory computing, where the computing units are placed directly inside the SRAM, and the results are stored in place. "We are the first in China to do digital compute-in-memory," a Houmo AI staff member said with certainty. Houmo even customized a "bFP16" precision format to find a new balance between performance and accuracy. The compute-in-memory architecture also brings a very high energy efficiency ratio. "During the inference stage, especially the decoding stage of large models, compute-in-memory can cut the overhead of data movement," explained a Houmo AI staff member. "Look at our chip, it only has 10 watts and can run 160 TOPS (INT8). The IO cost of traditional GPUs is too high."
Hanxu Technology, on the other hand, has chosen another technology route: MRAM compute-in-memory. This enterprise, incubated by the Applied Magnetism Center of Peking University, uses Samsung's 8nm process for tape-out, using MRAM (Magnetic Random Access Memory) as the compute-in-memory medium and SRAM as the cache. The advantage of MRAM lies in its non-volatility (data is not lost when power is off). "The video memory and computing units of traditional GPUs are separated, while we are truly integrated together," a Hanxu Technology staff member emphasized.
04. AI NAS: The "Greatest Common Divisor" of Edge Chips
The evolution of technology and products must ultimately be implemented in specific scenarios. In terms of application implementation, WAIC 2026 provided an unexpected answer: AI NAS. On the booths of almost every edge chip manufacturer, AI network-attached storage devices can be seen. Zhixin Technology cooperates with Meigao, SOPHGO launches with ecosystem partners, and Rockchip supplies to UGREEN/Ruisa... AI NAS has suddenly become the "greatest common divisor" of edge AI. The reason behind this is that NAS itself is a local data storage center. With the addition of AI computing power, it can realize the intelligent organization of local pictures/videos, natural language retrieval, and AI processing under privacy protection, without the need to upload data to the cloud.
AIPC is another major landing scenario. Zhixin Technology's P1 chip is equipped in Lenovo mini hosts (about 2,500 RMB after national subsidies), supporting the simultaneous operation of more than 20 agents; moreover, Zhixin Technology is also "the world's first ARM architecture SoC manufacturer that can directly install the standard version of the Windows ARM system" without the need for special adaptation by Microsoft. SOPHGO and Rockchip are also making efforts in the Xinchuang (IT application innovation) notebook field, adapting to domestic operating systems.
Embodied intelligence is opening the imagination ceiling for edge chips. Zhixin Technology and Iluvatar CoreX have cooperated to launch a robot controller, which performs object recognition and grasping based on the NPU; Hanxu Technology's MRAM chip has been adopted by Galbot, targeting the robotics track.
05. Boundary Dissolution: The "Cloud Migration" Path of Edge Manufacturers
The most intriguing trend at WAIC 2026 is that the boundary between the edge and the cloud is dissolving. Edge chips are beginning to go to the cloud in a distributed architecture, forming servers.
Starting from edge SoCs, Zhixin Technology has created an array server that can be equipped with up to 60 SoC chips. According to the introduction, each server integrates 60 small boards, and each board has only one P1 (CS8180) chip, 48GB (4*12GB) LPDDR5X memory (optional), and a system SSD, forming a "minimum computing unit." The whole machine is uniformly managed by a BMC processor. "A traditional server uses a large CPU for large tasks. We disassemble it, letting 60 small ones do their own small tasks," introduced a Zhixin Technology technician. A single P1 chip can run 6-7 channels of Honor of Kings or 16 channels of Douyin. With 60 chips stacked, the whole machine can support 360 concurrent game channels or 900 Douyin streaming channels. This means that edge chips are counterattacking the cloud with a distributed architecture. In scenarios such as cloud gaming, cloud phones, and Android cloud servers, a large number of lightweight, concurrent computing tasks do not require a single expensive Xeon CPU, but are more suitable for stacking and processing with low-cost, low-power edge SoCs. Zhixin Technology revealed that such array servers previously mostly used competitors' solutions, "and now they have basically all switched to our company."
Xindongli Technology's GPGPU also spans both ends. On the edge, it makes M.2/PCIe small cards, while on the cloud, it launches a board acceleration card integrating 12 AE7100E chips, compatible with the CUDA ecosystem. Then, 8 acceleration cards are loaded into a high-density server, which can support the deployment of large models with parameters from 400B to 1.6TB, and has been implemented in medical gene sequencing solutions. This distributed architecture of small chips provides a new solution for edge chips to go to the cloud.
SOPHGO is a typical example of another path from the edge to the cloud. This enterprise, which has been deeply cultivating the edge TPU field for nearly ten years, was once low-key due to sanctions in 2024. However, at WAIC 2026, its cloud product line has fully returned: the OpenClaw "Big Lobster" all-in-one machine equipped with 4 OAM modules and Hygon CPUs has a single-machine computing power of 1P (FP8); the cloud TPU acceleration card has been iterated to the second generation, and the third generation is about to be released; the world's earliest server-level RISC-V processor has also been implemented in the Shandong University cluster. "We started from the edge, but we will fight in both the cloud and the edge," said a SOPHGO staff member. Under the trend of large models, the demand for cloud computing power is obviously more vigorous than that of the edge, which is also the fundamental reason why edge manufacturers have to extend upwards.
The characteristic of this era is no longer simply comparing TOPS numbers, but a systematic competition of architectural innovation (3D stacking, compute-in-memory), form innovation (standardized interfaces for coprocessors), and scenario innovation (integration of edge, cloud, and endpoint). 3D stacking proves that the edge can run large models, compute-in-memory proves that low power consumption can support high computing power, and the 60-SoC array proves that edge chips can also do cloud tasks. Of course, the challenges remain real: rising DRAM prices compress profits, advanced process foundry is restricted, killer applications are still being cultivated, and ecosystem adaptation is far from perfect.