Author: Peng Cheng
In October in Shanghai, at the first-ever "Guoxin Exhibition" held during the China International Industry Fair, many people took photos of three data cards at the DF Compute booth: the world's first verification of a 3D chip cluster system, completion of training adaptation for mainstream large models in 7 days, and running through the full chain of chip-software-cluster in 24 months.
Viewed individually, each is a typical launch figure. Viewed together, the three figures point to three capabilities respectively: system-level verification capability, software adaptation speed, and industrialized delivery efficiency. The common focus of these three capabilities is another announcement made by the company at the Guoxin Exhibition: the 128-card cluster system is running stably, large-scale training cluster delivery has been achieved, and thousand-card-level cluster delivery will be realized by the end of the year.
Looking at the entire industry, over the past two years, domestic computing power chips have been released intensively, and single-card parameters have been constantly approaching overseas flagship models. However, there is a long engineering cycle between parameter release and scale delivery. Professor Wei Shaojun has deeply observed that current AI applications are updated rapidly on a weekly basis, and large model algorithms are iteratively upgraded on a monthly basis, whereas chip R&D iteration operates on an annual cycle, and once deployed, systems can run stably for 5 to 10 years. This severe imbalance in iteration pace poses extremely high requirements for chip design and system adaptation.
01. First, 7 Days, 24 Months: Three Facets of a Delivery
DF Compute emerged precisely with the goal of bridging this gap. The company was founded in Zhangjiang, Shanghai, in May 2024; completed its Series A+ financing at the end of April this year with a post-money valuation of CNY 12.275 billion, with the National AI Industry Fund listed as a shareholder; completed its joint-stock reform in September, and plans to launch Series B financing in the fourth quarter. Chairman Wei Shaojun is a tenured professor at Tsinghua University and Vice Chairman of the China Semiconductor Industry Association. The team originated from Tsinghua's nearly two decades of research accumulation in reconfigurable computing. Within two and a half years of its establishment, DF Compute has completed the full closed loop from chip R&D, full-stack software adaptation, to large-scale deployment of hundred-card-level training clusters, compressing the entire process into 24 months. How was this delivery achieved? The answers lie in these three figures.
First is the world's first verification of a 3D chip cluster system. Between lighting up a single card and deploying it at scale lies not only a quantitative difference but also a qualitative leap in engineering difficulty. Prior to this, 3D stacked high-compute chips had remained at the stage of papers and samples. As one of the key technologies for 3D stacking, the hybrid bonding process was used by Sony for image sensors around 2016, and in 2018, YMTC applied it to 3D NAND. For nearly a decade since then, the main application scenarios for this process have always been sensors and flash memory. Using the same process between DRAM and AI logic chips, and then forming a cluster for continuous large model training, has never been done before.
More critically, when high-compute chips are formed into a cluster, the problems will be amplified. With hundreds of chips training collaboratively, any issue with link stability, VRAM reliability, or temperature control of a single chip will be exposed during long-term continuous operation. For training clusters, 72 hours is a recognized threshold. Only under a sufficiently long continuous load can the weak links of the system be nowhere to hide. According to disclosures by DF Compute at the Guoxin Exhibition, the 128-card DF1000 training cluster has undergone 72 hours of uninterrupted continuous training, with training accuracy meeting standards, and has already undertaken training tasks for multiple large models such as Llama2-70B and Step 130B.
In terms of the supply chain, the DF1000 has completed a closed loop entirely on the domestic industrial chain, from chip design, 14nm wafer manufacturing, 3D hybrid bonding packaging, to packaging and testing. For the cluster side, switches and network cards directly adopt mature domestic products. The most important value of the DF1000 lies in achieving a fully domestic supply chain, rather than leading in a single performance metric. In the reality where the supply of advanced processes and HBM faces uncertainties, a fully domestic closed loop is itself a capability that needs to be verified. The subject of this verification is not only the chip but also the quality of the entire domestic supply chain in supporting large-scale training.
Second is completing the training adaptation for mainstream large models in 7 days. The only question customers truly care about is: can their models run, and at what cost? The figure disclosed at the Guoxin Exhibition is: the hundred-billion-parameter-level Step 130B large model completed training adaptation in just 7 days. In the past, when teams migrating domestic computing power performed cross-platform adaptation, it often required months of manpower investment, involving operator rewriting, accuracy alignment, communication tuning, and regression testing, which was the largest hidden cost for customers when selecting domestic chips. The 7-day adaptation turns "migration" from a project into a process.
Finally, running through the full chain of chip-software-cluster in 24 months. Under the industry's conventional pace, from chip tape-out, software adaptation, to cluster construction, it usually takes three to four years. DF Compute's path is three-line parallelism: chip design, compiler and operator library development, and cluster system architecture advancing synchronously and verifying collaboratively, rather than waiting for successful chip tape-out to start software, and waiting for software adaptation completion to build the cluster. From the company's establishment in May 2024 to the delivery of the first fully domestic large-scale training cluster, the entire process took 24 months.
The premise for parallelism to hold is that the certainty of each link is sufficiently high. After the DF1000 accelerator card was taped out and returned, full-specification tests including computing power, VRAM bandwidth, communication bandwidth, power consumption, and temperature were completed at once, and all 11 BF16 operator tests passed on the first try. The effectiveness of hardware-software co-design on the silicon wafer reduced rework in subsequent links. On the cluster side, a standardized delivery process of "deployment-joint debugging-stress testing-trial training-acceptance" has been formed, making the entire process from infrastructure adaptation to possessing large model training capabilities controllable.
02 Where Does the Efficiency Come From: Architecture, R&D, O&M, and Supply Chain
Part of the explanation for this efficiency can be found at the engineering organization level, but the more fundamental answer lies in the choice of technology route. For practitioners focusing on domestic computing power, to see the true strength of a computing power company, one mainly looks at three things: Total Cost of Ownership (TCO), delivery capability, and software ecosystem. DF Compute supports these three through the technology route of near-memory computing combined with software definition.
In terms of architecture, 3D stacked near-memory computing breaks through the "memory wall" bottleneck. Traditional high-end AI chips adopt a separate architecture of "computing core + external HBM". The bandwidth bottleneck must be compensated by advanced processes and more complex packaging. Data is transported over long distances between computing units and storage units, causing power consumption and costs to rise continuously. The choice of DF1000 is to fundamentally change the connection between storage and computing: directly bonding the DRAM wafer on top of the logic wafer, with copper pads aligned for direct connection, without bumps or interposers in between. The interconnect pitch is compressed from tens of microns to the sub-micron level, achieving a single-chip memory access bandwidth of 6.4TB/s. This bandwidth level is higher than the official specifications of mainstream AI chips using HBM VRAM solutions: 3.35TB/s for H100, 4.8TB/s for H200, and 5.3TB/s for MI300X. The DF1000 achieves HBM3E-level bandwidth on a 14nm process without using HBM. The bandwidth advantage continues to be amplified in the roadmap: the DF2000, planned for release in the fourth quarter of this year, will increase the memory access bandwidth to 15TB/s, exceeding the 8TB/s of B200.
In terms of R&D model, a unified technology stack achieves cross-generational reuse, reducing adaptation costs. In the traditional model, chips, basic software, and cluster systems often belong to different manufacturers. Cross-architecture and cross-platform adaptation requires repeated investment, and each generation of hardware upgrade means re-adaptation of the full chain. DF Compute's approach is to independently develop everything from chip architecture to compilers, operator libraries, collective communication libraries, distributed training frameworks, and cluster scheduling and O&M tools. Data shows that DF Compute has fully independently developed the full-stack autonomous CAAP software stack, covering compilers, operator libraries, distributed communication libraries, training frameworks, and one-stop development tools. It is fully compatible with mainstream deep learning frameworks. Open-source large models such as DeepSeek, Qwen, and STEP can be quickly migrated and deployed, reducing the landing and adaptation costs of domestic computing power chips. Since the chips, software, and clusters come from the same team, each generation of iteration does not require cross-manufacturer re-adaptation, and the operator optimization and scheduling strategies accumulated in the previous generation can be directly reused for the next generation of products. The software-defined architectural attribute amplifies this advantage. Traditional AI chips have fixed hardware functions; during chip tape-out, which operators are supported and what data paths are used are already burned into the silicon. However, the Tile array and data paths of the software-defined chip hardware can be configured by software, and the same chip can execute different computing structures through different software configurations. Thus, the focus of adaptation shifts from hardware to the software layer. For the adaptation of new models, the CAAP compiler only needs to map it into a data flow graph and expand it for execution on the Tile array. Core operators are already covered by the operator library, requiring only incremental optimization. After a chip generation change, the hardware execution mode remains consistent, and the compiler optimization, operator implementation, and scheduling strategies polished in the previous generation can be directly carried over without rebuilding around the new hardware.
In terms of O&M, "full-stack isomorphism + intelligent O&M" reduces cluster O&M costs. For clusters with heterogeneous hardware and mixed architectures, the workload of troubleshooting, tuning, and compatibility maintenance grows linearly with scale. DF Compute's full-stack isomorphic technical system, integrated with the intelligent scheduling, fault self-healing, and full-dimensional monitoring systems equipped in the cluster, enables a limited O&M team to support the stable operation of a 128-card cluster. The gap in O&M efficiency will be further amplified when the cluster scale reaches thousands.
In terms of the supply chain, a fully domestic supply chain resolves deliverability. The route relying on advanced processes and overseas high-end devices has its capacity expansion cycle constrained by external capacity and control lists. Relying on a fully domestic mature process supply chain, the DF1000 is not subject to overseas technology control constraints. It features fast capacity expansion, controllable delivery cycles, and a secure, autonomous supply chain, enabling rapid response to the market's computing power construction needs. The confidence to sprint towards a thousand-card-level cluster by the end of the year stems precisely from this.
Of course, this route has its own costs. The yield of 3D stacking decays multiplicatively as the number of layers increases. The more layers and the larger the capacity, the more obvious the cost pressure, and the yield rate is the ceiling of 3D stacking. Trading a mature process for a performance window is essentially using engineering complexity to hedge the process generation gap. This exchange is cost-effective under current industrial chain conditions, but it is not a free lunch.
03 Demand in Place, Near-Memory Computing Power Enters the Window for Scaled Delivery
The advantages of the route must ultimately be tested in the market, and the signals given by the market are clear enough. According to data from the CAICT, in the first quarter of 2026, domestic AI computing power demand increased by 417% year-on-year, while the supply growth rate was 128%. High-end chips have entered a seller's market, with cards in short supply.
On the demand side, it is mainly driven by two forces. First is the deepening of Xinchuang. As the requirement for computing power autonomy extends to core systems in industries such as finance, telecommunications, and energy, the requirement for the computing power foundation has been upgraded from "usable" to "usable at scale". Second is the accelerated landing of industry AI. Large models are penetrating from internet companies to industry scenarios. Out of considerations for data security and business latency, industry customers' training and inference loads increasingly require private deployment. These needs make high-cost-performance, scalable domestic computing power a rigid demand. More critically, the load structure is also changing. Pre-training is concentrated in top large model manufacturers and national-level computing power centers, while the larger increment lies in the fine-tuning and inference of industry models. These loads are not sensitive to single-card peak parameters, but are more sensitive to Total Cost of Ownership, delivery cycles, and long-term stable operation, which exactly falls into the strengths of the near-memory computing solution.
On the supply side, DF Compute's product hierarchy covers different scale demands from single cards to entire clusters. The Dianfeng DF1000 accelerator card is the smallest delivery unit, the Qingyuan QY100 is an 8-card single-machine server, the Tuoyu TY64 is a 64-card liquid-cooled super node with a single-node computing power of 33 PFLOPS (BF16), and the Huisuan series covers 128-card, 256-card, and 512-card clusters for overall delivery. The 128-card cluster system is running stably, large-scale training cluster delivery has been achieved, and thousand-card-level cluster delivery will be realized by the end of the year. The iteration pace has also been scheduled: the DF2000 is planned for release in the fourth quarter of this year, with a BF16 computing power of about 1000 TFLOPS and a memory access bandwidth of 15TB/s; the DF3000 is planned for release in the fourth quarter of 2027, with indicators doubling on this basis.
For the domestic computing power industry, the value of this route goes beyond a single company. It provides a replicable paradigm: not relying on the most advanced processes and HBM, basing on a fully domestic supply chain, trading architectural innovation for system efficiency, with low investment, fast landing, and iterability. When more and more industry loads need to run on an autonomous and controllable foundation, the industrial space for this paradigm will be further opened up.
04 Conclusion
Looking back, running through the full chain from chip to cluster in 24 months is a complete self-proof of the near-memory computing technology route: the efficiency advantages in the three links of system-level verification, software adaptation, and industrialized delivery ultimately converged into the result of "fully domestic training cluster delivery". Domestic computing power has thus crossed the critical node from parameter release to industrialized verification.
How far this route can actually go, Professor Wei Shaojun himself gave a restrained answer: the long-term ceiling of the entire software-defined near-memory computing route is still the process technology. He frankly stated that if domestic advanced processes achieve a breakthrough in the future, the company will introduce more advanced processes at the first opportunity. The significance of this route is to win a time window for domestic computing power, not to declare that the process is no longer important.
Scaled application after verification is the real test. From 128 cards to a thousand cards, every time the scale steps up, the pressures of stability, yield rate, O&M, and delivery organization will appear at a different magnitude; the business loads of real customers are more complex than the model combinations during the trial training stage; and whether this route can continuously deliver on performance promises in long-term evolution still needs time to answer.
Over the past few decades, the core question answered by the domestic chip industry has always been "can it be manufactured"; the three figures suggest that the industry proposition has changed to "can it be delivered and can it be used". The time gap of years versus weeks between chips and algorithms cannot be made up by single-point parameters. DF Compute's route proves for the first time that it can be filled with system efficiency. When the iteration speed of chips begins to keep up with the speed of application updates, the mismatch between domestic computing power and AI industry evolution will truly see the possibility of bridging for the first time.