Author: Feng Ning
Over the past two years, the spotlight in the memory industry has been firmly on HBM—the massive demand generated by AI large model training has made high-bandwidth memory the most sought-after track in the semiconductor industry, with prices soaring and supply falling short of demand. However, entering 2026, another technological concept is moving from the fringes of the industry to center stage: CXL.
So, what is CXL, and how is it carving out a new niche in the memory market dominated by industry giants?
01. CXL Takes Center Stage
For any technology to achieve large-scale explosion, there must first be a sufficiently painful trigger. The trigger for CXL is a price list that leaves data centers unable to sit still.
Let's look at a set of data:
Since the second half of last year, global memory chip prices have continued to climb. Data from East Money Choice shows that in the international market, the average contract price of 16Gb DRAM chips used for DDR5 rose from $4.8 per chip in May 2025 to $37.5 in May 2026, an increase of 681% over the year. During the same period, the average selling price of mainstream DDR5 16GB consumer memory modules surged from about 800 RMB in mid-2025 to over 4,000 RMB currently, an increase of more than 4 times within half a year.
In the server sector, the price of 256GB DDR5 memory modules has exceeded 50,000 RMB. Data shows that the unit price of 64GB DIMM modules has cumulatively increased by 3.5 times from Q3 2025 to Q1 2026, and the total increase is expected to expand to 5 times by Q3 2026.
What the author wants to discuss here is not "the price increase itself," but the structural nature of the price increase. The underlying driver of this round of memory price hikes since 2025 is the siphoning effect of AI servers on DDR5—large model inference requires massive memory to hold huge model parameters and KV Cache, while the number of memory channels in server CPUs is limited, which can only be met by stacking high-capacity modules. When the demand side is the collective upgrade of millions of servers, and the supply side is that the big three memory manufacturers have already allocated the bulk of their capacity to HBM, the supply-demand gap for DDR5 is not cyclical, but structural.
It is precisely in this gap that CXL has transformed from a "next-generation technology" into a "current solution".
Before understanding CXL, let's first understand a definition. NUMA (Non-Uniform Memory Access) is a memory architecture design suitable for multiprocessor systems. In a NUMA system, each CPU (more accurately, each NUMA node) has its own "local" memory, and the latency to access this memory is relatively low. Accessing the "remote" memory of other nodes requires crossing the NUMA bus, resulting in poorer latency and bandwidth. This is because it cuts the most precious resource, memory, into isolated islands both physically and logically.
CXL (Compute Express Link) technology is a new type of high-speed interconnect technology designed to provide higher data throughput and lower latency to meet the needs of modern computing and storage systems. It was initially launched jointly by Intel, AMD, and other companies, and has received extensive support from companies including Google and Microsoft. This means that enterprises do not need to fully equip every CPU with high-priced, large-capacity DDR5 local memory. Instead, they can centrally deploy standardized memory resource pools via the CXL bus, enabling computing nodes to elastically call memory on demand.
Therefore, the main battleground for CXL is in the fields of AI, high-performance computing, and data centers.
Since its release in 2019, the CXL protocol has undergone multiple versions of evolution, and the CXL protocol is closely related to PCIe versions.
CXL 1.0 was released in March 2019, built on PCIe 5.0 technology. CXL 2.0 was released in November 2020, also based on PCIe 5.0, and introduced memory pooling, switching functions, persistent memory, and security features. CXL 3.0 was released in August 2022, based on PCIe 6.0, with single-lane bandwidth increased to 64 GT/s, and introduced the Fabric concept, supporting multi-level switching, true memory sharing, and device peer-to-peer communication. CXL 3.1 was released in November 2023, featuring incremental updates based on CXL 3.0, enhancing fabric scalability and Trusted Execution Environment (TEE) support. CXL 3.2 was announced in December 2024, optimizing the monitoring and management of CXL storage devices and extending security through the Trusted Security Protocol (TSP). The CXL 4.0 specification was released in November 2025, achieving a data rate of 128 GT/s.
It is no exaggeration to say that CXL has brought a revolution to data centers.
First, according to the definition of the CXL Consortium, the standard uniformly supports three types of devices: 1. High-speed cache devices, such as smart NICs; 2. General-purpose computing and acceleration chips, covering CPUs, GPUs, DPUs, SoCs (System on Chip), and various AI/FPGA accelerators; 3. Memory expansion controllers, covering DRAM, new types of persistent memory, and NAND flash memory, usually used as memory buffers to expand bandwidth or capacity. At this stage and even in the next 2-3 years, the most core and realistic value of CXL lies in expanding server memory resources at a more economical cost and improving data transmission efficiency. But the deeper significance can be seen in the evolution roadmap of CXL.
Second, as mentioned above, CXL 2.0 and subsequent versions introduced memory pooling and sharing capabilities, which means CXL 2.0 allows the memory resources of multiple servers to be pooled through switches and dynamically allocated to different computing nodes on demand. This is a key step for this technology to move from a single machine to a cluster. However, to achieve rack-level or even data center-level global pooling, it is necessary to wait for the large-scale commercialization of CXL 3.0 and higher version hardware (which supports Fabric multi-level switching).
Third, the industry is currently exploring NVDIMM (Non-Volatile Dual In-line Memory Module) and solutions based on new storage media (such as MRAM and ReRAM). In the future, there may be hope to use them as remote persistent memory in conjunction with the CXL interface.
Fourth, as CXL is gradually implemented, there is another evolutionary direction with more room for imagination: its deep integration with Infrastructure Processing Units/Data Processing Units (IPU/DPU). Currently, when CPUs and DPUs collaboratively process storage and network tasks, data needs to be copied multiple times between their memories, consuming CPU cycles and increasing latency. CXL supports the establishment of a unified, cache-coherent shared memory domain between the CPU and DPU. This means the DPU can directly read the data to be processed in the CPU memory, and write it back directly after processing, eliminating explicit data movement. This capability will improve the efficiency of tasks such as storage offloading, compression/decompression, and encryption/decryption by an order of magnitude.
In summary, CXL is not just an interface standard, but a philosophical shift that transforms memory from the "private property" of the CPU into a data center-level "public resource".
02. Meta Reveals Its Wounds
In CXL memory systems, the Memory eXpander Controller (MXC) is the absolute core component. It is a high-performance Application-Specific Integrated Circuit (ASIC) or System on Chip (SoC), located on the CXL memory module (such as E3.S or PCIe AIC form factors).
Recently, at the ISCA 2026 International Symposium on Computer Architecture, Meta unveiled its self-developed Vistara custom chip solution. This is a CXL ASIC specifically designed to reuse DDR4 memory from decommissioned servers. By connecting DDR4 memory modules from old servers to new-generation DDR5 servers to build a shared memory pool, it has been implemented in hyperscale infrastructure covering millions of servers. A paper published simultaneously by Meta shows that this solution can reduce the number of servers required for some AI inference workloads by up to 25%, and decrease the average latency of distributed cache by 29%.
In the paper, Meta revealed a widespread resource mismatch problem in data centers: the expected service life of servers is usually 3 to 5 years, but the physical lifespan of server-grade DRAM chips can reach 7 to 10 years. This means that a large amount of DDR4 memory with still good performance will be left idle or even scrapped as the entire machines are decommissioned.
More severely, in Meta's own infrastructure, about 40% of the servers—on a scale of millions—are unable to continue carrying new AI workloads due to memory capacity limitations. At the same time, a massive amount of DDR4 memory remains idle. Against the backdrop of soaring DDR5 memory prices and tight supply, this dilemma of "old memory sitting idle while new memory is unaffordable" represents a huge waste of resources for hyperscale internet companies with annual capital expenditures reaching tens of billions of dollars.
In addition, cloud providers such as Google have also begun deploying CXL in data centers and are installing controllers to manage data traffic between CPUs and large external memory pools. NVIDIA, on the other hand, plans to support the CXL 3.1 standard in its Vera CPU to be launched later this year, a move regarded by the industry as the largest-scale real-world test of CXL to date.
Therefore, the "reuse" of CXL comes at the perfect time.
03. CXL: The Era Has Arrived
Currently, there are only a handful of manufacturers that can provide mature commercial products, which can be mainly divided into two categories: one is independent interconnect chip design companies, and the other is memory original manufacturers attempting vertical integration.
Regarding interconnect chip design companies, Montage Technology, relying on its profound accumulation in DDR4/5 buffer chips, has extended into the CXL memory controller field and established a first-mover advantage. It released its first CXL MXC chip supporting the CXL 2.0 standard in May 2022. In 2024, it completed the R&D of the mass production version of its first-generation CXL MXC chip. In January 2025, the chip successfully passed the CXL 2.0 compliance test and was included in the first batch of CXL 2.0 compliant supplier lists published by the CXL Consortium. The memory manufacturers Samsung Electronics and SK hynix, which were also selected during the same period, used Montage Technology's MXC chips in their tested products. In September 2025, the company released a new generation of MXC chip, the M88MX6852, designed based on the CXL 3.1 standard, and began sending samples to major customers for testing. In addition, interface IP leaders Microchip, Marvell, Rambus are also major competitors in this field.
As early as August 2022, Microchip announced the expansion of its serially connected storage controller product portfolio, launching the new CXL-based SMC 2000 series intelligent storage controllers. Marvell's CXL strategy is more like an aggressive acquisition strategy. In 2022, Marvell announced the acquisition of Tanzanite in an all-cash transaction to enhance its cloud-optimized CXL product portfolio. In January this year, Marvell announced that it had reached a definitive agreement to acquire advanced PCIe and CXL switch chip supplier XConn Technologies for approximately $540 million. Rambus has also launched its own CXL 3.1 controller chip, but its larger business remains in IP licensing.
As for memory original manufacturers, they mainly procure CXL controllers and integrate them into memory modules before delivering them to customers. Previous reports indicated that Samsung named its CXL DRAM module CMM-D and planned to start mass production of CXL 3.1 standard memory products as early as Q4 2026. SK hynix completed customer certification for its CXL 2.0 standard products in 2025 and exhibited the CMM-DDR5 CXL memory module for AI servers. Micron Technology launched the CZ120 memory expansion module based on the CXL 2.0 standard as early as 2023.
However, by July 2026, the situation took a critical turn. According to South Korean media reports, Samsung Electronics, SK hynix, and Micron Technology have all scaled back or abandoned their in-house commercialization plans for CXL controllers. Among them, Micron has closed its in-house R&D department and adopted Primemas's solution; SK hynix terminated its in-house project, with the team shifting to the PIM (Processing-In-Memory) field; and Samsung removed its in-house controller from its commercialization roadmap, retaining only cutting-edge R&D.
The fundamental reason for the collective shift of the big three manufacturers is perhaps the concern that their in-house high-end CXL controllers would cause "cannibalization" with their core source of profit—general-purpose DRAM modules. At the same time, data center customers are also more inclined to adopt a "disaggregated" structure, which is to procure third-party controllers and general-purpose DRAM separately for combination to reduce costs.
Memory original manufacturers have not abandoned the CXL technology itself, but rather abandoned the commercialization plans for in-house controllers, turning instead to procure products from professional chip design companies. This strategic shift has actually strengthened the market position of independent chip design companies such as Montage Technology.
Industry analysis believes that 2026 is the starting point for large-scale deployment of CXL, and it is expected to enter the first year of large-scale commercial use of CXL in 2027. Given the mass production of server CPU platforms supporting CXL 3.0, more advanced memory pooling solutions will be gradually implemented, and the penetration rate of CXL in data centers is expected to rise rapidly in the coming years.