Introduction: The Backside Power Delivery Network (BSPDN) is regarded by the industry as a key enabling technology for the 2nm node and below—it moves the power delivery network to the back of the wafer, freeing up front-side routing resources, improving dynamic voltage droop by approximately 10 times, and reducing the required metal layers from 10-12 to 7-8. However, research from institutions such as TSMC and imec reveals a paradox: while total power consumption is decreasing, the temperature of local hotspots on the chip may actually rise by as much as 14°C. Where exactly does this extra heat come from?
I. Thermal Path Restructured: The Silicon Substrate, a "Free Heat Spreader," Is Ground Away
To understand the source of the extra 14°C, one must first see clearly what backside power delivery has changed.
In the traditional frontside power delivery structure, the transistors are topped with over a dozen metal layers and sit on a silicon substrate approximately 775 micrometers thick. During chip packaging, the device side faces down. Heat travels from the transistors, passes through the thick silicon substrate, and then reaches the heat sink via the thermal interface material. The thick silicon substrate plays two roles here: vertical heat conduction and, more importantly, lateral spreading, distributing the heat from local hotspots over a larger area, effectively providing the transistors with a free heat spreader.
Backside power delivery leaves the devices in the middle: the front side features interconnect layers solely for signals, while the back side has the newly fabricated power delivery metal layers. Describing this structure, imec researcher Miles noted that the heat-generating devices are "sandwiched" between the frontside interconnects and the backside metal. More critically, the back of the wafer needs to be thinned to 1-3 micrometers—grinding away 99.8% of the 775-micrometer thickness, precisely removing that silicon plate responsible for lateral heat spreading.
The thermal conductivity of silicon is approximately 140 W/(m·K), whereas that of silicon dioxide is only 1.4 W/(m·K). After thinning, only low-thermal-conductivity dielectric and metal layers remain around the hotspots. Heat has nowhere to spread laterally; it can only accumulate in place and is forced to squeeze out in a single direction. Herman Oprins, head of the thermal modeling team at imec, pointed out that the additional temperature rise mainly stems from two aspects: the reduced lateral heat spreading capability due to the thinned silicon substrate, and the fact that the silicon carrier and bonding interfaces have entered the main thermal path leading to the cooling solution.
II. Three Sets of Data Point in the Same Direction: Temperature Rise Is Not an Isolated Case
Currently, there are three main sets of publicly available quantitative evidence. While their sources and conditions vary, their directions are highly consistent.
The first set comes from an imec paper presented at IEDM 2024. Based on the real power consumption distribution of an 80-core server SoC, they performed thermal simulations with a 1-micrometer resolution on a 112-square-millimeter model. The conclusion is: compared to the frontside power delivery structure, the hotspot temperature in the backside power delivery structure can be up to approximately 14°C higher. The paper attributes the cause to the interaction between the additional thermal resistance and the reduced heat spreading capability of the backside power delivery itself.
The second set comes from package-level simulations by National Yang Ming Chiao Tung University. Their metric is the maximum temperature: 57°C for the frontside power delivery structure, rising to 80°C when switched to backside power delivery. Sources of thermal resistance include the high thermal resistance of the frontside back-end-of-line layers, the hybrid bonding layer introduced by the wafer backside process, and substrate thinning.
The third set comes from a multi-scale modeling study. Analysis of the CPU hotspot area shows that the temperature of the backside power delivery structure is approximately 45% higher than that of the frontside power delivery.
The description of Intel's PowerVia test chip is frequently cited as a counterexample. However, this chip is an energy-efficient core test chip using the Intel 4 process plus PowerVia, still utilizing FinFETs. It is not on the same scale as kilowatt-level GAA high-performance computing chips, so the two do not constitute a direct contradiction.
III. Cooling Solutions Are Moving from Outside the Package into the Silicon Die
In response to this challenge, the industry chain has launched countermeasures at multiple levels.
The design end is taking the lead. Miles outlined two pathways: maximizing the metal density of the backside power delivery network to let the metal layers handle local lateral heat spreading, and increasing the via density in the frontside back-end process to reduce thermal resistance toward the heat sink. Going further, thermal management is becoming an explicit constraint during the placement stage—standard cell placement, the clustering degree of high-power modules, and nano-TSV layout are all being re-evaluated.
Cooling structures, on the other hand, are undergoing a migration from outside the package to inside the silicon die. TSMC demonstrated a direct silicon water-cooling solution at ECTC 2025: fusion-bonding silicon-based micro-coolers etched with microchannels to the back of the chip, bypassing the thermal interface material. With a total power consumption exceeding 2.6 kilowatts, the temperature rise is kept within 63°C, and the backside power density of the logic chip exceeds 7 W/mm².
The solution announced this year by the Korea Advanced Institute of Science and Technology (KAIST) goes a step further, etching micrometer-scale water channels directly inside the silicon substrate. Single-phase cooling with room-temperature water can handle 2000 W/cm², keeping the chip core temperature below 100°C, without the need for expensive nano-surface modifications or diamond substrates.
Diamond materials represent another path that is more expensive but faster. Akash Systems delivered the first batch of NVIDIA H200 servers equipped with diamond cooling solutions in February 2026. Official data shows that the GPU hotspot temperature is reduced by 55-60°C, running at full frequency throughout, with a 15% performance improvement.
IV. Perspective: Thermal Management Is Shifting from Back-End to Front-End Processes
The absolute amount of heat is indeed decreasing, and the original intention of backside power delivery is being realized. However, the cost of increased cooling difficulty and the power saved are two separate accounts that need to be kept distinct.
I am not overly concerned about the cooling technologies themselves—microfluidic channels, direct silicon water cooling, and diamond; the numbers along these lines already show that there are solutions to remove the heat. What concerns me is the shift in the location of these solutions: they are moving from outside the package into the package, into the substrate, and into the silicon die itself. This means thermal management is transforming from a system-level process into a foundry process. Once a process enters the foundry, its pace of advancement is no longer determined by the iteration rhythm of data centers, but by yield, cost, and process maturity.
The last time the interconnect structure underwent a change of this magnitude was in the 1990s when aluminum was replaced with copper. After that change, interconnects shifted from a supporting role to the leading role. This time, thermal management might be pushed into the spotlight. Transistors can continue to shrink, but if power cannot be delivered in and heat cannot be dissipated out, the performance on paper cannot be realized.
Source: Compiled from online reports