At 2:00 AM, the lights are still on in a meeting room of a chip company in Zhangjiang. On the screen, a regression verification task has been queued for four hours: EDA licenses are fully occupied, the read/write speed of the storage array is approaching its limit, and dozens of servers are idling while waiting for data. The engineer stares at the progress bar; what they fear most is not an error message, but "waiting another three hours." Because in three hours, another batch of simulation tasks will flood in; after that come the tape-out window, customer sampling, and mass production milestones. It takes three to five years for a chip to go from project initiation to mass production, yet the golden window the market leaves for it is often less than three years.
Nights like this are not rare in the semiconductor industry. We are accustomed to imagining the "chip breakthrough" as a power fantasy: a sudden technological breakthrough that changes everything overnight. But in the real semiconductor industry, breakthroughs rarely happen with a single decisive blow. Computing power, storage, networking, tools, licenses, scheduling, data, security... if any single link falls behind, it can lead to prolonged waiting. Many people fail to realize that there is another invisible battlefield for chips, named "time."
Companies that have gone through complete chip-making cycles are increasingly aware of what "time" means. Huawei is a typical example. Over more than 20 years of chip-making practice, from early exploration to Kirin and Ascend, from repeated cycles of design, verification, and starting over, to designing and mass-producing 381 chips based on the Tau Scaling Law over the past six years, what remains is not just a series of products, but also a wealth of engineering experience on how to shorten R&D cycles and reduce system waiting times.
However, the experience accumulated by a single company can only generate greater industrial value if it is transformed into capabilities that can be reused by more companies. Thus, the question shifts from "how to make a better chip" to: can the experience bought with time and cost help latecomers wait less and avoid some detours?
Let us start from the progress bar at 2:00 AM and together understand this "time war" of chip-making.
The Time Dilemma: The Ultimate Battlefield for Chips
Objectively speaking, although companies like Huawei have made certain achievements in the chip field, the long-term dilemma haunting China's overall semiconductor industry still persists. There have been numerous discussions in the industry surrounding this dilemma. But what most discussions overlook is that time is a critical factor constraining China's chips, and it is one of the very few factors that can be altered.
Constrained by the realistic environment, the development of China's chips started with entirely headwinds: over 95% of EDA software relies on imports, and core materials such as high-end lithography machines, photoresists, and special gases also depend on external supply. Restricted by this special situation, China's semiconductor capacity is concentrated in low- to mid-end chips, with massive centralized and redundant construction. The supply of high-performance CPUs, GPUs, advanced storage, and high-end RF chips is severely insufficient.
However, China is not short of attempts to march towards high-end chips. Why do these attempts repeatedly fail? A key constraining factor is time. The R&D budget for an advanced chip often exceeds USD 1 billion, and the more advanced the process node, the more massive the upfront investment. From a time perspective, it often takes three to five years, or even longer, for a chip to go from project initiation to mass production. But the problem is that the effective market lifespan of mainstream chips is often under three years. Chips that are finally mass-produced at enormous cost often face the embarrassment of being obsolete upon market entry.
For example, the famous 908 Project took seven years from initiation to production, but its 0.9μm process after successful mass production was already 4 to 5 generations behind international mainstream standards, completely lacking market competitiveness.
For decades, China's chips have repeatedly faced the cycle of "introduction - falling behind - re-introduction - falling behind again," always struggling to make their products truly competitive and build a positive flywheel of market and technology.
Therefore, the true dilemma of China's chips lies not in whether a specific chip is advanced, but in whether there is still market value by the time this sufficiently advanced chip is built.
So, how can this deadlock be broken? There is only one answer: race for time. At all costs, race for time in every link and process. One cannot wait for conditions to mature or for everything to be ready; one must adapt to the war of time in the rapidly evolving industry and turn time into one's own weapon.
For example, according to relevant data, Chinese chip companies spend about 65% of their R&D cycle on verification and simulation. In other words, a massive amount of time is spent on continuous trial and error, and constantly discovering problems. Chip design involves a massive number of elements: architecture, RTL, functional verification, synthesis, placement and routing, timing closure, power analysis, physical verification, DFT, and tape-out. Each stage may undergo multiple rounds of complex repetitive verification. Ultimately, massive time costs are consumed in a time maze full of unknowns. Every minute and second that passes is like a countdown to this chip being abandoned by the market.
How can we escape this prison-like time dilemma?
The Time War Borne by Huawei
If there is any Chinese company that has truly borne this time war and ultimately won, it must be Huawei.
From K3V2 and Mate 7 to Kirin 980, Huawei truly completed the entire process from catching up to commercialization, and then to global top-tier standards, enduring a survival test near a desperate situation. In this process, Huawei's understanding of chip-making evolved from single-point devices and single parameters to the co-convergence of software and hardware, architecture, process, and system, distilling three experiences: "time, system, and continuity." The accumulation of these capabilities realized the return of Kirin chips and the rise of Ascend computing power, and also led to the eventual birth of the Tau Scaling Law, which replaces traditional "geometric scaling" with "time scaling."
Another remarkable achievement of Huawei's chip capabilities is the pioneering of the supernode route.
UnifiedBus Ascend 950 is Huawei's latest-generation AI computing power platform, comprising two chips, 950PR and 950DT, with single-card computing power already reaching 2.87 times that of NVIDIA's H20. Achieving abundant and stable acquisition of AI computing power based on supernodes + cloud has become the mainstream choice in the era of intelligent agents.
But from a more macro perspective, what we need is not for Huawei to learn to outrun time, but for the entire Chinese semiconductor industry to win the race against time. Chip autonomy is also not about the success of a single chip, but the popularization of advanced semiconductor R&D capabilities.
Then, the only way to break the deadlock going forward is to turn the "time war" borne by Huawei into a rallying call for China's chips.
Distilling the Experience of the Time War into the Cloud
Chip-making experience is a very complex and broad matter, extremely difficult to distill into specific capabilities and platforms. But precisely because of this, it must be distilled, reused, and promoted.
Huawei's chip-making experience has been gradually distilled into large-scale computing pools, hybrid clouds, high-performance storage, unified scheduling, security, and a second computing power plane. By productizing over 20 years of chip-making practice, Huawei attempts to turn the experience of "where waiting is most likely and where bottlenecks occur most easily" into reusable cloud infrastructure capabilities.
We can look at some examples to see how Huawei's chip-making experience is distilled in the cloud.
Chip R&D has a very obvious "computing power tide": Normally, it might only use 30% of resources, but on the eve of large-scale regression verification or tape-out, computing tasks will suddenly surge. Huawei Cloud undertakes this peak-valley variation with large-scale computing pools, and further organizes computing power, networking, and storage more tightly into a rapidly schedulable resource pool through UnifiedBus UB, Qingtian Bare Metal, and EVS Ultra-fast Cloud Disks, achieving minute-level provisioning and elastic reuse.
The true bottleneck in chip R&D lies in efficiency, where phenomena of devices, computing power, and licenses being mutually uncoordinated often occur. To this end, Huawei Cloud can provide an integrated chip design and simulation platform, uniformly managing EDA applications, licenses, cluster resources, and budget configurations, supporting hybrid cloud scheduling, simplifying and clarifying complex project management, and rescuing the time dissipated in mutual waiting across different systems.
There is another common waste in chip R&D, called "machines waiting for data." EDA simulation repeatedly reads and writes massive amounts of small files; once storage cannot keep up, even the most powerful CPU can only idle. Huawei Cloud SFS Turbo can scale to the PB level; in HPC-type file systems, public specifications can scale on demand up to 30 million IOPS and 2 TB/s throughput. IOPS can be understood as "how many data retrievals can be processed per second," while throughput is like "how wide the data highway is"—the former solves the frequent reading and writing of massive small files, and the latter accelerates the transportation of large batches of data; essentially, both aim to minimize the time expensive computing power spends waiting for data.
The aggregation of these capabilities in the cloud is a path to transforming Huawei's chip-making experience into shared industry experience.
The way humanity fights against time is to reduce repetition and improve efficiency.
China's Chips Must Race Against Time
China's chip endeavor is a tragic and heroic expedition setting sail in a sea of bitterness.
To break out of the vicious cycle of "introduction - falling behind - re-introduction," we need to consolidate successful experiences so that more companies can avoid detours. Turn the explorations completed in the darkness of the past into a broad avenue that Chinese chip companies can walk directly. China's chip endeavor certainly needs powerful computing power, advanced EDA tools, and a stable supply chain system, but it even more needs a comprehensive system that can assemble them all and continuously translate them into chip R&D efficiency.
On this path, Huawei Cloud has already provided chip companies with comprehensive core capabilities and holistic support.
In terms of EDA Cloud, based on a distributed computing power foundation and security protection system, Huawei Cloud provides a cloud-based R&D environment for deployable and adaptable EDA tools. The core value is not simply "moving software to the cloud," but providing infrastructure capabilities such as elastic computing power, high-performance storage, secure collaboration, and on-demand usage.
In terms of elastic computing power, EDA Cloud supports on-demand acquisition and release of resources, allowing companies to scale up quickly during critical periods and reduce idle resources during flat periods; in terms of tool and job management, it can place adapted EDA applications, cluster resources, and project budgets into a unified environment for collaborative management. For cross-regional R&D teams, Huawei Cloud can also provide a consistent R&D and security environment through multi-Region, dedicated lines/VPNs, and unified resource management, reducing the time loss caused by redundant construction and environmental differences across regions.
In OPC scenarios, Huawei Cloud provides elastic, on-demand computing clusters, shortening the traditional IT construction cycle of several months to the weekly level. At the same time, through a combination of capabilities such as the YMS (Yield Management System) and AI quality inspection, semiconductor solutions are extended from "accelerating R&D" to "improving manufacturing quality."
On the computing power side, capabilities such as UnifiedBus UB, Qingtian Bare Metal, and EVS Ultra-fast Cloud Disks further transform computing, networking, and storage from "operating in silos" into a more unified resource pool: Resources can be rapidly scheduled, provisioned at the minute level, and elastically reused. According to the planning caliber of existing solutions, the goal is to further reduce the amortized cost of resources; in some HPC optimization tasks, higher task throughput and cost-effectiveness are also the optimization directions. For chip companies, what truly matters is not buying a few more servers, but how many more rounds of effective simulations can be run in the same day.
On the storage side, Huawei Cloud continuously improves throughput and concurrency capabilities for massive data read/write and layout aggregation scenarios in EDA/OPC. In the public specifications of SFS Turbo HPC type, if expanded according to business needs, it can reach up to 30 million IOPS and 2 TB/s throughput. Coupled with capabilities such as data direct access and near-compute caching, there is only one goal: move data one less time, wait one less minute, and snatch back a little more time for chip R&D.
Looking to the future, Huawei Cloud's vision is not just "creating another EDA software mall." As Tau Design gradually toolizes new chip design methods, and Hanqing and HPDK promote open interoperability of domestic EDA, Huawei Cloud has the opportunity to use the cloud as the foundation for computing power and operations, gradually connecting these capabilities with cloud-based EDA/OPC, unified scheduling, high-performance storage, and secure environments. The truly critical next step is to continue solving the cloud deployment, license adaptation, and security boundaries of EDA software, and further connect the Fab's PDK, process rules, and manufacturing capabilities.
In other words, Huawei Cloud hopes to explore moving from "EDA on the cloud" further towards "one-stop cloud-based chip operations," enabling more efficient collaboration of domestic computing power, tools, R&D data, PDK, and even manufacturing capabilities within the same R&D system. True autonomy for China's chips means not just owning our own chips, computing power, and EDA tools, but also possessing an R&D system that can organize them and continuously build the next chip. The ultimate goal remains only one—to help China's chips win this race against time.
"Leave the complex things in the cloud, and give time back to the engineers"—the chip breakthrough may not have too many grand narratives; doing simple things to the best of our ability is already enough.
Time is our friend, and so is victory.