Every leap in large models is reshaping the design paradigm of AI chips. According to Statista data, the global AI market size has grown from USD 94.8 billion in 2020 to USD 254.5 billion in 2025, and is expected to reach USD 1.675 trillion by 2031. In China, the AI chip market size was approximately CNY 142.5 billion in 2024, and is projected to reach CNY 1,336.8 billion by 2029, with a compound annual growth rate (CAGR) of up to 53.7% from 2025 to 2029, far exceeding the global average. However, the larger the market, the higher the threshold. The exponential increase in design complexity, the increasingly prominent "memory wall" and "power wall," and the uncertainty in supply chain security—these three hurdles stand before every AI chip player. Where is the way to break through?
Recently, Yang Kai, Marketing Director of Brite Semiconductor (Shanghai) Co., Ltd. (hereinafter referred to as "Brite Semiconductor"), a one-stop custom chip and IP service provider, delivered a keynote speech at the 2026 Hardcore Chip Summit of the IICIE Exhibition and accepted an exclusive interview with Xinshiye. From self-developed IP to silicon platforms, and from edge AI to automotive-grade chips, the answers to breaking through are worth exploring.
01. The "Three Major Challenges" in the AI Era
According to a market report by MarketsandMarkets, North America will dominate the global AI market in 2026 with a share of approximately 42.3%, while the Asia-Pacific region will experience the fastest growth, with a projected CAGR of 34.5% from 2025 to 2032. The growth of China's AI chip market is mainly driven by three factors: domestic substitution policies promoting the increase of the localization rate of data center hardware, the explosive demand for large model training and inference, and the rapid popularization of edge AI chips. Among them, "domestic substitution" is regarded as a huge incremental opportunity in the next five years, while "edge AI" possesses strong explosive power.
According to estimates by industry institutions, the market size of edge AI chips in the Chinese market will exceed CNY 21 billion in 2026, a year-on-year growth of 38%, and the overall market size of edge AI for the whole year is expected to reach CNY 866.1 billion. However, the challenges accompanying the opportunities are equally clear: the explosion of design complexity: trillion-parameter models and emerging architectures make traditional design methods unable to meet timeliness requirements; the "dual-wall" bottleneck: the "memory wall" and "power wall" make data transmission a bottleneck for computing power; supply chain security: there is uncertainty in the acquisition of capacity, high-end EDA, and key IP. Facing new paradigms, large markets, and high challenges, edge AI chip design must seek more efficient, more agile, and more reliable new methods.
02. From General-Purpose to Application-Specific: Customization Becomes a Must
Diversified application scenarios are showing an unprecedented trend of customization, which poses stringent requirements for chips in terms of intelligence, differentiation, cost control, R&D cycle, and security. In terms of architecture selection, although general-purpose chips aim for broad compatibility, it is difficult to optimize the energy efficiency ratio for specific scenarios; whereas custom ASICs achieve scenario-based optimization through deep integration and software-hardware co-design. Although the initial NRE (Non-Recurring Engineering) costs are relatively high, they can significantly reduce peripheral components and lower BOM (Bill of Materials) costs. Facing these complex demands, Brite Semiconductor has chosen a diversified layout for chip design paths.
Traditional modular design facilitates individual testing and replacement, but suffers from bottlenecks of high system latency and power consumption; the SoC (System on Chip) architecture relies on silicon-level interconnects and unified clock and power domain designs to eliminate the losses caused by off-chip communication; some SoC chips go a step further by integrating design to balance the flexibility of modularization and the advantages of high integration. It can be said that this multi-dimensional architectural evolution and differentiated demand are exactly the solid market foundation for Brite Semiconductor's "one-stop custom chip service."
03. Consolidating the IP Core: The Hard Power of the YOU Series IP
Customization is the direction, and IP is the foundation. The self-developed YOU series IP of Brite Semiconductor has formed a complete matrix, covering more than ten categories including DDR, SerDes, PCIe, MIPI, USB, ONFI, eMMC, TCAM, PLL, ADC, Crypto, RF, and IO. It has further been precipitated into the YouSiP silicon platform, forming scenario solutions such as IoM, Audio, Vision, IoT, and AP, all of which have passed tape-out verification or mass production. In terms of key indicators and core capabilities, Brite Semiconductor's series of IP demonstrates extremely strong hard power:
DDR—Adapting to the high bandwidth requirements of chips;
PCIe—Protocol stack optimization, adapting to various custom chips;
SerDes—Supporting multi-rate, multi-protocol, and Die-to-die interconnects, providing high-throughput, low-latency physical layer interconnect solutions between chips;
MIPI—Low-power and high-speed transmission, meeting the visual data transmission requirements of high pixels and high frame rates;
USB—Implementing a complete mixed-signal and OTG connection IP solution;
TCAM—Significantly alleviating the memory wall, reducing power consumption and latency, suitable for edge retrieval and massive data matching scenarios;
PLL—Adapting to low-jitter system requirements, ensuring stable chip operation;
ADC—High effective accuracy and system performance planning, ensuring the accuracy and efficiency of data acquisition.
In terms of domestic process adaptation, in 2025, several high-speed interface IPs on various process platforms of Brite Semiconductor have completed verification and have been licensed to multiple customers. The core competitiveness of Brite Semiconductor is manifested in a complete self-developed IP matrix, sufficient silicon tape-out verification, excellent PPA (Power, Performance, Area) performance, IP + platform synergy advantages, and one-stop supporting services.
04. Strengthening the Platform Ecosystem: The "Two-Way Synergy" Between IP and ASIC
The uniqueness of Brite Semiconductor lies in that it is both an IP provider and an ASIC customization contractor, with the two businesses deeply synergizing: after completing domestic process silicon verification, IP can be directly used for ASIC customization, avoiding process matching risks; mature IP reuse can shorten development cycles and reduce design costs; the YouSiP platform connects software and hardware, balancing standardized reuse and personalized needs; the integration pain points of ASIC projects reversely optimize the PPA and debugging capabilities of IP; ultimately, a unified team achieves full-chain one-stop delivery.
In terms of delivery, Brite Semiconductor provides "ODM + OEM" solutions, covering product definition, architecture and RTL (Register Transfer Level) design, physical layer design, to wafer manufacturing, packaging and testing, and even logistics, while the application market is always controlled by the customers.
The platform value is ultimately verified by landing cases. Currently, YouSiP-Audio integrates a complete voice interaction link, which can realize voice processing, recognition, and broadcasting offline, such as smart voice terminals like smart meeting boxes, smart voice elevators, and smart social TVs; YouSiP-Vision integrates high-speed interfaces such as MIPI, PCIe, LPDDR3, and USB to realize visual recognition and processing such as target object detection and scene information analysis.
05. Irreplaceable: The Core Value of Design Service Companies
Facing the product line sinking of general-purpose SoC giants and the self-developed chips of leading system manufacturers, the value of design service companies is more prominent. Lowering the landing threshold: outputting integrated "IP + ASIC" services, so customers do not need to build large-scale chip design teams; avoiding tape-out risks: reusing silicon-verified IP to improve the first-time tape-out success rate; domestic process adaptation: solving integration difficulties such as power domains and memory bandwidth, adapting to edge mass production needs; balancing customization and standardization: making differentiated modifications based on the YouSiP platform to control NRE costs; bridging the algorithm gap: connecting upper-layer data processing needs with lower-layer hardware physical implementation to solve engineering problems such as operator mapping and power consumption optimization.
06. In Conclusion
From IP to platforms, from edge to automotive-grade, the way Brite Semiconductor breaks through is essentially a path of "thickening certainty." It uses silicon-verified self-developed IP to reduce customers' tape-out risks, uses a platform-based ecosystem to carry scenario-based customization needs, and uses one-stop services to shorten the cycle from concept to mass production.
In the era of intelligent computing, competition will ultimately fall on "who can make chips faster and more stably." Consolidating the IP core and strengthening the platform ecosystem are not only technical choices to cope with the "three walls," but also strategic answers to establish coordinates in the two incremental markets of domestic substitution and edge AI.
The content of this article is all from public information and does not constitute any investment advice.