Author: Junxi
Recently, Apple was reported to be evaluating a return to the commercial server market, with proposed products targeting AI inference, considering the use of its in-house M-series chips, and evaluating the introduction of NVIDIA's NVLink Fusion interconnect technology.
Apple has previously used its self-developed chips for private cloud computing to handle cloud tasks for Apple Intelligence. If it sells servers to external customers, the products will need to enter other enterprises' data centers and integrate with the customers' network, software, and operations and maintenance systems. For a company with chip design capabilities, commercial servers remain a business that requires organizing an external supply chain.
In the following week, interconnect suppliers successively disclosed new progress. On September 23, Cadence announced a demonstration of the UALink solution on TSMC's N3P process, providing silicon-verified interface designs for chip companies to adopt open interconnects. On the same day, network chip company Cornelis further introduced its product roadmap for next-generation AI systems, planning to offload part of the data processing to NICs and switch chips.
For self-developed chips to enter servers, it is necessary to decide which interconnect architecture to adopt and then find partners capable of providing interfaces, switches, and connectivity components. The recently disclosed interface verifications, product roadmaps, and sampling plans are all centered around these procurement choices.
01. Switch Market: Generation Upgrades and Capacity Expansion in Parallel
Statistics released by IDC on September 11 show that in the second quarter of 2026, the global data center Ethernet switch market revenue reached USD 12.3 billion, a year-on-year increase of 64.5%. This figure counts switch equipment, covering hyperscale, service provider, and enterprise data centers, reflecting that data exchange between servers has formed a considerable scale of procurement demand.
In the same statistics, the proportion of 800GbE products in data center Ethernet switch revenue has risen from 35.9% in the first quarter to 41.2% in the second quarter. While the market size is growing, revenue is also concentrating on products with higher port speeds. After the switch ports are upgraded in speed, the accompanying switch chips and connectivity components must also meet new signal transmission requirements.
A report by Dell'Oro on September 3 pointed out that in the second quarter, switch sales for AI back-end networks exceeded those for front-end networks for the first time. The front-end handles communications such as business access, while the back-end mainly connects acceleration servers, serving massive data exchange during training and inference processes. Dedicated networks built for computing tasks are changing the network procurement structure in data centers.
Within the scope of AI back-end Ethernet, 800G equipment already accounts for the vast majority of shipments and revenue this quarter, and 1.6T products have also begun sampling, with expanded shipments expected in the second half of the year. Current procurement and next-generation verification are proceeding simultaneously. Suppliers need to ensure the delivery of existing equipment while preparing new products for the customers' next round of system design. Whether the R&D schedule can align with the customers' capacity expansion schedule directly affects which round of procurement the products can participate in.
Connecting accelerators and switch equipment also requires cables, optical interconnect components, and chips that recover high-speed signals. Credo sells such products. On September 1, the company announced its latest quarterly results for the period ended August 1, with total revenue reaching USD 479 million, a year-on-year increase of 114.7%. These connectivity products have become a business of considerable scale in the server supply chain.
Credo's products cover both copper and optical connections, as well as forms such as chips, modules, and cables. Which computing chip a server adopts will not eliminate the corresponding connectivity needs; however, the transmission distance, interfaces, and cabling methods used in each generation of systems differ, which will change the specific component combinations. Therefore, independent suppliers need to develop products in tandem with customers' system designs, striving for new customers while maintaining entered system projects.
Dell'Oro expects that the AI back-end switch market will remain supply-constrained for at least the next one to two years. This provides conditions for manufacturers with delivery capabilities to expand their business and also makes buyers pay more attention to whether equipment can be delivered on schedule. Even if a cluster has already obtained acceleration cards, it still cannot operate at the originally planned scale if the network supporting infrastructure is not completed; the delivery rhythm of interconnect components needs to be arranged synchronously with server procurement.
The agency also judges that Ethernet sales in the AI back-end currently come mainly from cross-server and cross-cluster connections, and applications for tighter accelerator interconnects will begin to emerge in the second half of the year. The product positions that suppliers can strive for are extending into the inside of the rack. What needs to be solved here is not just transmitting data faster, but also how accelerators exchange results and collaboratively execute the same task.
02. What Kind of Interconnect Support is Needed for Self-Developed Chips
Inside a server or a group of closely collaborating accelerators, chips require connections with higher bandwidth and lower latency. The NVLink Fusion reportedly evaluated by Apple, and the UALink verified by Cadence this time, are both related to the needs at this level. They determine what kind of interconnect architecture the accelerators adopt, while interface IP, switch chips, and connectivity components are responsible for integrating the corresponding architecture into the products.
On September 10, d-Matrix announced that its next-generation Raptor chip will adopt NVLink Fusion and integrate with NVIDIA's MGX rack design, with supply expected to begin in the fourth quarter of 2027. The company focuses its self-development on inference chips, leaving part of the interconnect and rack design to existing platforms. For companies adopting this path, product development needs to align with the platform's interface, system design, and verification requirements.
UALink, on the other hand, provides another way to organize the supply chain. It is a set of accelerator interconnect standards. Chip design companies can adopt interfaces that support this standard and then cooperate with corresponding switch chip and system manufacturers. The IP provided by Cadence is a pre-designed module that can be integrated into customers' chips; completing silicon verification on a specified process can reduce the customers' work of implementing it from scratch based on protocol specifications.
Such interface designs are directly related to the manufacturing process. For companies preparing for tape-out, whether the standard is open is just one condition; they also need to see if there is adoptable IP on the target process and whether the switch chips can keep up with the system development schedule. The progress disclosed by Cadence this time on the N3P process provides specific chip design conditions, and subsequent verification in the customers' complete products is still required.
Once an interface enters the chip design, subsequent replacements will involve adjustments to the chip, packaging, and board. From this perspective, the time for interconnect vendors to win customers is usually earlier than the formal procurement of servers. Products that participate in the definition and pass verification first are more likely to enter the bill of materials for this generation of systems; even if other suppliers subsequently launch products with similar performance, they still need to re-acquire the customers' design and verification resources.
System manufacturers are also arranging products for different routes. On September 23, H3C introduced an architecture using UALink inside the cabinet and Ethernet between cabinets at the Apsara Conference forum: first organizing multiple accelerators into closely collaborating computing units, and then connecting these units into larger clusters. The company also stated that the UniPoD S80000 series will follow multiple mainstream interconnect protocols, retaining choices for different chip combinations.
The same set of standards can reduce redundant design, but it does not mean that acceleration cards from different manufacturers can already be mixed and used directly. H3C mentioned at the conference that the coexistence of multiple chips and interconnect protocols increases cross-vendor adaptation costs. Beyond the interfaces, drivers, communication software, and fault handling still need to be verified together. As server buyers have more choices, the software and hardware combinations that system manufacturers need to maintain also increase accordingly.
For companies preparing to adopt self-developed chips, accessing existing platforms can reuse the supporting infrastructure already established within them; adopting open standards and selecting suppliers independently can retain more combination space while taking on more integration work. Both sides are striving for next-generation server designs, and what customers need to compare is the performance, cost, and delivery schedule of the entire solution.
03. Independent Suppliers Striving for Next-Generation Servers
Cornelis announced USD 205 million in financing on September 14, with funds to be used for expanding products, production, and customer deployments. The company already has network technology used in hundreds of data centers. At that time, the CN5000 was shipping, and the CN6000 had been sampled to customers, with expanded supply expected in the fourth quarter. Entering the in-rack interconnect market requires continuing to develop new products on the basis of this business.
According to the roadmap further disclosed on September 23, Cornelis's next-generation CN7000 plans to support interconnect standards such as UALink, providing a combination of NICs and switch chips. Its role is to provide the hardware and software to realize interconnects. After customers adopt open standards, they still need to purchase such products to connect the accelerators.
The added selling point of this product line for Cornelis is enabling network equipment to handle a portion of data processing. For example, when multiple accelerators jointly train a model, the results calculated by each need to be aggregated and then redistributed; if NICs and switch chips can complete partial merging as the data passes through, it can reduce the redundant sending, receiving, and processing work at the accelerator end. The company also plans to support inference cache migration to reduce the overhead of host participation in communication.
The company calls these features the Active Compute Fabric and plans to configure programmable processing cores so that some new operations can be added through firmware updates. For customers, the value lies in reducing the time already purchased accelerators spend waiting for data. Specific benefits depend on tasks and system configurations, and the utilization improvements currently published by Cornelis mainly come from model calculations.
According to its latest schedule, the CN7000, which fully implements this roadmap, targets customer deployment in 2028. This generation of NICs is planned to work on standard Ethernet networks, and can add functions when paired with its own switch chips. Customers can therefore verify the NICs first and evaluate whether to adopt more supporting products after confirming the benefits. The customer relationships accumulated by Cornelis previously can provide opportunities to access projects, but the new architecture still needs to complete its own introduction process.
Delos Data chooses to start from the interface where accelerators access the network. Its Data Interface released on September 15 provides three forms: chiplets, near-package optics components, and boards, targeting accelerators as well as devices like CPUs and memory. It also needs to cooperate with the interconnect protocols and systems selected by customers, with a focus on coordinating data exchange between different devices and handling some faults at the interface.
The three forms correspond to different stages of cooperation. Chiplets require participation in the design and packaging of next-generation accelerators, while boards provide system-side access methods. Therefore, Delos must face both chip design companies and customers building servers and clusters; whether it can enter a project depends on when the customers finalize the chip, packaging, and network solutions.
As the number of accelerators increases, a problem with one chip or one link may cause other devices to wait for data. Delos hopes to have hardware interfaces detect faults and manage recovery to reduce the impact on the entire task. Currently, its cluster platform is already used in existing infrastructure, and new server products are planned for sampling by the end of 2026.
In this release, Delos also added pre-deployment design and simulation tools to the cluster platform. Customers can use PCIe cards to verify real workloads, test interfaces through pre-tape-out simulation, and compare different connection methods and fault scenarios in cluster-level models. This enables chip design, network layout, and software tasks to be evaluated together in advance, allowing customers to troubleshoot adaptation issues in the solution before deciding to build.
On the same day, Delos disclosed over USD 100 million in financing, explicitly stating that the funds will be used to expand its software and hardware engineering teams, product development, and sales. Verification tools also belong to the products it provides to customers. For such companies, R&D investment needs to cover software and system support beyond interface chips, and customer onboarding work will continue until the testing, deployment, and operation stages.
On September 21, Qualcomm, Lumentum, and Corning announced a joint demonstration plan for optical inter-chip connections, hoping to extend high-density connections to tens of meters via optical fibers. In this solution, Qualcomm provides the inter-chip interface subsystem, Lumentum provides the optical engine, and Corning provides the fiber optic connections. The electrical interface on the chip side and the subsequent optical signal transmission need to be co-designed. This combination is aimed at future near-package and co-packaged optics systems and is currently still in the proof-of-concept stage.
Buyers are also controlling the complexity of the combinations. Natalie Serrino, co-founder of inference infrastructure company Gimlet Labs, stated in an interview published on September 21 that the company hopes to adopt two to four types of chips in a single data center and find combinations that can be repeatedly deployed. Different chips can take on the computations they are good at respectively, but increasing the types of chips will also increase the work of connection and software adaptation.
04. Conclusion
Whether Apple will return to the commercial server market remains to be confirmed. The interconnect market is expanding, and products from various suppliers are still at different stages. Going forward, whether the products can pass customer verification, operate stably with different chips, and be delivered on schedule will affect the progress of these companies in securing orders and expanding deployments.