Introduction
On August 6, 2026, AMD announced its intention to acquire Taalas, a Canadian AI chip company, planning to integrate its technology into future accelerator roadmaps and develop system-level solutions with Instinct GPUs.
Taalas was founded in 2023 by Ljubisa Bajic, co-founder of Tenstorrent. Conventional AI chips typically manufacture general-purpose computing hardware first and then load model weights from external memory into the chip at runtime; Taalas, however, attempts to reverse this by baking the base weights of specific models directly into the hardware during the chip design and manufacturing stages. The company claims that its first chip, the HC1, built on the 6nm process of TSMC (Taiwan Semiconductor Manufacturing Company), baked the base weights of Llama 3.1 8B (approximately 8 billion parameters) into a technology demonstrator chip.
This approach ties efficiency potential to cycle risks: models can be revised in a matter of months; will the chips manufactured for them be delivered and recoup their costs in time?
I. Why Does "Building Chips for Models" First Collide with the Semiconductor Cycle?
Models can be revised in weeks or months, whereas chips must go through design freeze, manufacturing, packaging, testing, and delivery. By the time the chip is ready, the original model it targeted may have already been upgraded.
Figure 1 | As the model iterates from A to D, the chip is still in manufacturing and delivery.
Application-specific chips reduce runtime control overhead and data movement by pre-defining more computation paths and model information, but the trade-off is direct: once the model undergoes significant changes, the corresponding hardware design may also need modification. Taalas is attempting to shorten exactly this revision time. Its pending patent application describes an approach: reusing most of the underlying circuitry and only adjusting the upper-level metal connections responsible for fixing the model weights.
These metal layers also need to be formed through photolithography masks. The patent application states that the cost of modifying upper-level masks is only 1/10 to 1/100 of that for modifying lower-level masks; an EE Times interview noted that changing the model on the HC1 requires modifying only two masks. The CEO of Taalas also stated that converting a model into the RTL code required for chip design takes about a week. This can reduce the design time and mask costs for model revisions, but the cycles for wafer manufacturing, packaging, and testing still cannot be bypassed.
II. Why Don't Enterprises Switch When Some AI Chips Already Approach NVIDIA GPU Performance?
However, the cycle is not the only barrier for AI chips to enter production systems. Some general-purpose AI chips have already approached the overall system performance of NVIDIA GPUs in specific tasks and tests, yet enterprises still do not easily switch platforms because of this. What is truly difficult to replace is the entire production system: frameworks, operator libraries, compilers, multi-GPU communication, and deployment tools all need to be re-adapted, and team expertise must be rebuilt. Switching chips often means slower time-to-market, along with increased costs and risks.
This production system does not inherently belong to GPUs; rather, it gradually formed around CUDA through long-term technological evolution. GPUs initially served graphics rendering, and their massive parallel computing capabilities were later proven suitable for neural networks. NVIDIA introduced CUDA in 2006, opening GPUs to general-purpose computing; after AlexNet used GPUs to train ImageNet in 2012, the demand for GPUs in deep learning grew rapidly. Since then, cuDNN, frameworks, compilers, multi-GPU communication, and debugging tools have continuously accumulated around CUDA, ultimately forming today's highly entrenched and difficult-to-replace production system.
Alternatives to bypass CUDA have been continuously evolving. Huawei uses CANN to support Ascend, Google builds its own hardware and software ecosystem with TPU and XLA, and AMD uses HIPIFY to migrate some CUDA code. However, switching platforms still requires re-verifying function libraries, actual performance, and multi-GPU operations. There is also a more radical approach: reducing reliance on the general-purpose software stack itself. FixyNN hardwires parts of CNN networks into hardware; HNLPU further attempts to bake large model weights into chip interconnects. Taalas, on the other hand, has unveiled the HC1 technology demonstrator chip, claiming it baked the base weights of Llama 3.1 8B during manufacturing. This is no longer just about replacing CUDA with an alternative; it is about shifting a portion of the computation originally determined by software into hardware in advance.
III. Why Does CUDA Make the GPU Path Increasingly Difficult to Bypass?
The difficulty of switching platforms is only the surface level. The deeper barrier of CUDA is that it has become deeply embedded in the model development and deployment processes. Models ultimately need to be implemented as specific computations such as matrix multiplication and attention, executed by GPU kernels. For a new model to reach production, it must not only run but also integrate low-precision computing, multi-GPU parallelism, and deployment. Existing kernels, function libraries, and communication tools can be directly reused; when key components are missing, teams must write their own operators and kernels, re-verify accuracy, performance, and stability, and continuously maintain them as GPUs and frameworks are upgraded.
Figure 2 | Models enter GPU (Graphics Processing Unit) kernels from architectures and operators, and are then constrained by memory and multi-GPU execution; the mature GPU path, in turn, shapes model engineering choices.
This engineering cost also shapes model design in return. The computing power, VRAM, and interconnects of GPUs define the performance boundaries, while the CUDA ecosystem has distilled optimization methods adapted to these constraints into mature tools. To run faster and more efficiently on existing GPU clusters, teams will adjust model parallelism, compress the KV Cache, alter expert routing, or rewrite attention computations. Over time, model engineering and the GPU hardware and software stack have become increasingly deeply adapted to each other. But since models can accommodate hardware, another approach is to reverse this and make the hardware more thoroughly accommodate the models. Taalas is taking exactly this path.
IV. How Far Has Taalas Pushed Chip Specialization?
To understand Taalas, one can first look at a fundamental trade-off in AI chips: the more general-purpose a chip is, the easier it is to adapt to different models; the more specialized it is, the higher the efficiency potential, but the greater the pressure to revise the chip when models change. Taalas is taking the highly specialized end of this spectrum: it even bakes model weights into the chip, thus gaining higher efficiency while also having to solve the revision issues caused by rapid model iterations.
Central Processing Units (CPUs) allocate more circuitry to branching, caching, and control, excelling at handling unpredictable programs. Graphics Processing Units (GPUs) use massive parallel units to process AI computations and can still switch tasks via software, but their efficiency highly depends on kernels, data layout, and multi-GPU communication. Tensor Processing Units (TPUs) further fix matrix computation paths, allowing compilers to schedule execution in advance, while still being able to load various models after the chip is manufactured. There are already many specialization routes in the market; chips like Trainium, Gaudi, Groq, Cerebras, and Etched have achieved varying degrees of specialization from computing units and dataflows to chip form factors, but most still load model weights after the chip is manufactured.
Taalas, however, directly builds chips for specific models. The HC1 baked the base weights of Llama 3.1 8B during manufacturing; if the model undergoes significant changes, the chip may also need to be re-customized or even re-manufactured.
Figure 3A | CPUs and GPUs retain more runtime choices; TPUs and other AI ASICs pre-fix more computation paths.
Figure 3B | Two patent applications from Taalas describe a connectivity mesh for fixed weights and a "model core + fine-tuning portion," respectively; EE Times reports that the on-chip SRAM of the HC1 can store fine-tuning weights or the KV Cache. Inputs and outputs still need to flow.
V. What Does AMD Want to Buy by Acquiring Taalas?
The core capability AMD likely values is baking model base weights directly into the chip. When generating text, GPUs need to continuously read massive amounts of weights from VRAM, making performance and energy consumption highly susceptible to memory bandwidth limitations. Taalas's patent approach is to hardwire a portion of the weight selections directly into the metal interconnects, allowing the chip to read fewer weights and move less data during runtime, thereby improving generation speed and energy efficiency for bandwidth-bound inference. In the company's internal tests, the HC1 achieved a single-user speed of 16,960 tokens per second when running Llama 3.1 8B.
Fixing the base weights does not mean the model is completely locked down. Another patent retains a small number of rewritable areas on the chip for fine-tuning methods like LoRA; the on-chip SRAM of the HC1 can also store fine-tuning parameters and the KV Cache. In other words, what is fixed are the base weights of Llama 3.1 8B, while prompts, context, and some fine-tuning parameters can still be adjusted.
However, these performance advantages still lack large-scale physical validation. The only publicly available chip currently is the HC1 running Llama 3.1 8B, and the performance data mainly comes from the company's internal tests; the HC1 uses 3-bit and 6-bit parameters, and the model quality in the company's internal tests is lower than GPU baselines. The solution for DeepSeek R1-671B remains in the simulation stage, with the company estimating the need for about 30 different custom chips; the second-generation 4-bit solution also awaits physical validation.
Viewed within AMD's product lineup, what Taalas fills is likely the capability to "build chips for specific models." Its value primarily lies in trading specialization for higher inference performance and energy efficiency, but this advantage is not equally significant for all workloads: if the bottleneck mainly comes from weight movement, the benefits of fixed weights are more pronounced; if a large amount of time is spent on the KV Cache, intermediate results, or inter-chip communication, the benefits will diminish.
VI. How Can Model-Specific Chips Recoup Their Costs?
Figure 4 | Specialization investments for named models must be amortized before demand declines; reusable platforms and IP can be recouped across generations.
Whether such chips can recoup their costs mainly depends on two variables: how long the model can run stably, and how large the call volume is. Taalas envisions keeping the same "chip + model" set running continuously for a year, using the savings in inference costs to cover the investments in customization, manufacturing, deployment, and operations.
However, this calculation currently lacks real customer data. The single-user speed of 16,960 tokens per second published by Taalas comes from the company's internal tests; the cost advantage is also mainly based on company estimates and still awaits validation with volume products.
What AMD is truly taking on is the model cycle risk: GPUs are responsible for catching up with rapidly changing models, while specialized chips bet on already stable, large-scale workloads. If the model changes first and the chip hasn't run enough volume, the costs may not be recouped in time.
References:
[1] AMD: AMD Acquires Taalas to Advance Compute Solutions for Rapidly Growing AI Inference Market (2026-08-06).
[2] Taalas: Products (HC1 Technology Demonstrator).
[3] Taalas: The Path to Ubiquitous AI (2026-02-19).
[4] Taalas Patent Application: Large Parameter Set Computation Accelerator Using Configurable Connectivity Mesh (US20250123802A1, Pending).
[5] Taalas Patent Application: Computing Architecture with Model Core and Fine-Tuning Portion (US20250238726A1, Pending).
[6] EE Times Interview: Taalas Specializes to Extremes for Extraordinary Token Speed (2026-02-19).
[7] CPU, GPU, and CUDA Official Documentation: CUDA Programming Guide; GeForce 8800 GPU Architecture Overview (2006-11); Intel 64 and IA-32 Architectures Optimization Reference Manual.
[8] Pre-AlexNet GPU Neural Network Research: Large-scale Deep Unsupervised Learning using Graphics Processors; Deep Big Multilayer Perceptrons for Digit Recognition.
[9] Krizhevsky et al.: ImageNet Classification with Deep Convolutional Neural Networks.
[10] Chetlur et al.: cuDNN: Efficient Primitives for Deep Learning.
[11] Dao et al.: FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness.
[12] Huawei Ascend: CANN Commercial Version 9.0.0 Development Documentation.
[13] Google TPU / XLA Documentation: In-Datacenter Performance Analysis of a Tensor Processing Unit; TPU Architecture; XLA Architecture.
[14] AMD: HIPIFY Documentation.
[15] Programmable AI Accelerator Documentation: AWS Trainium Architecture; Intel Gaudi 3 AI Accelerator White Paper; Graphcore IPU Hardware Overview.
[16] Specialized AI Architecture Documentation: Groq Tensor Streaming Processor; SambaNova Dataflow Architecture; Cerebras Wafer-Scale Engine; d-Matrix Corsair AI Platform; MatX One.
[17] Positron Documentation: Atlas Inference System; Positron’s $230M Funding Led By Financial Trading Firms; Asimov.
[18] Etched: Etched is Making the Biggest Bet in AI (2024-06-25 page archive).
[19] NVIDIA: Getting Started with Deep Learning Performance.
[20] Whatmough et al.: FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning.
[21] Liu et al.: Hardwired-Neurons Language Processing Units as General-Purpose Cognitive Substrates.
[22] Model Adaptation to GPU Cases: Megatron-LM; Llama 2; DeepSeek-V3 Technical Report; Insights into DeepSeek-V3: Hardware for AI Architectures.
[23] Inference Workload and Bottleneck Papers: PagedAttention; Speculative MoE; Fast and Memory-Efficient Video Diffusion; DistServe; Efficiently Scaling Transformer Inference; Atom: Low-Bit Quantization for Efficient and Accurate LLM Serving.
[24] AMD: Form 10-K (Fiscal Year Ended 2025-12-27) (Filed on 2026-02-04).
[25] MLCommons: MLPerf Inference v5.1 Results Comparison (2025).
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