At the 2026 World Artificial Intelligence Conference (WAIC), several rows of cabinets on Huawei's booth were connected together, with 1,024 Ascend accelerator cards collectively referred to as "a single machine" — the Atlas 950 SuperPoD. Meanwhile, NVIDIA turned 72 GPUs into a purchasable full-rack platform, Google designed topologies separately for training and inference, and AMD turned the full rack into an open reference design. The nomenclature is not unified, and product boundaries differ, but the basic unit of AI competition is shifting from a single card to a larger system.
Organizing hundreds or thousands of accelerators into a single system means that every difficult task in communication, scheduling, fault recovery, and delivery must be resolved by someone. The more a vendor absorbs these challenges for the customer, the more likely it is to seize platform control, bargaining power, and profits. Consequently, the focus of AI competition has shifted from single-card specifications to the delivery capability of the entire system.
What Is a Strongly Interconnected Domain?
It can be understood as a group of accelerators capable of high-frequency, low-latency communication. The more the chips within the domain work collaboratively like "a single large card," the more efficient model partitioning, expert routing, and memory access become; beyond this boundary, communication typically has to traverse the slower data center network.
The first threshold for SuperNodes lies here as well: as the number of cards increases, the effective computing power must not drop too quickly. When tasks are split across more cards, communication, synchronization, scheduling, and fault recovery all consume theoretical computing power; doubling the number of cards does not necessarily double the task output.
In the past, AI systems often used 8-card servers as the basic unit, scaling between servers via the data center network. Following the popularity of large models, long contexts, and Mixture of Experts (MoE) models, a single model is partitioned across more chips. Expert routing, parameter synchronization, and Key-Value (KV) Cache transfers have become increasingly frequent, meaning expensive compute units spend more and more time waiting for data.
Consequently, the industry has moved from multi-card servers to rack-scale systems, and then to Pods (multi-cabinet units) and multi-cabinet SuperNodes [1]. The divergence among Huawei, NVIDIA, Google, and AMD lies in: how large the scope for high-frequency communication should be—whether it should remain within the server and rack, or expand into a cross-rack strongly interconnected domain; and who should design, deliver, and maintain this equipment.
Figure 2 | From multi-card in a single machine to full-rack, Pod/multi-cabinet, and SuperNode clusters, the system boundary continues to expand.
Huawei, NVIDIA, Google, and AMD Provide Four Different Answers
Beyond the table, let us look at their approaches. NVIDIA turns the full rack into a standard product for direct sale; Google achieves integration within its own cloud relying on self-developed chips, networking, compilers, and cloud scheduling; AMD delegates more integration work to partners in an open ecosystem; and Huawei coordinates compute, cross-rack interconnects, memory, and software through full-stack engineering. Facing the same system challenges, the four companies have presented four distinct product forms.
Huawei Has Pushed the Strongly Interconnected Domain to Multiple Cabinets
Now that 72 GPUs can already collaborate closely within a single cabinet, the remaining question is: why should this collaboration stop at the cabinet door?
Instead of waiting to catch up on a single-card basis, Huawei chose to trade a larger interconnected domain for total computing power and memory scale. The previous generation 384-card SuperNode has been deployed in over 750 sets, covering more than 20 industries; the Atlas 950, on the other hand, showcased a real 1,024-card machine, officially announcing a 256 TB global unified memory addressing space, TB-level NPU interconnects, and a 3-microsecond round-trip latency [5][6]. This design pulls a portion of the high-frequency cross-server and cross-cabinet communications—which would otherwise repeatedly traverse the data center network—into the same cross-rack strongly interconnected domain; external scaling and data access for the SuperNode still rely on the data center network.
Figure 3 | Huawei's approach changes the communication boundary: more high-frequency communications are kept within the same cross-rack strongly interconnected domain.
This roadmap is directly related to the supply environment Huawei faces. Xu Zhijun once publicly stated that there is still a gap in China's semiconductor manufacturing process, and sustainable computing power must be based on the actually available processes, continuing to improve computing power through a "SuperNode + cluster" system architecture [7]. The parts that cannot be made up by single-card process technology are transferred to interconnects, software, power supply, liquid cooling, and reliability, to be absorbed through systems engineering.
Unified Addressing Is Only the Starting Point
Pushing the strongly interconnected domain to a thousand cards yields one of the most direct benefits: a larger address space. The 256 TB unified addressing announced by the Atlas 950 brings memory distributed across different devices and different hierarchies into a single addressing system, allowing software to uniformly discover, address, and schedule these resources.
Figure 4 | Unified addressing expands the scope of resource visibility and schedulability, but does not eliminate memory hierarchies.
However, unified addressing does not eliminate memory hierarchies. Local HBM, remote HBM, host DRAM, and storage are still at different physical locations, and the switching hierarchies and media the data passes through are also different; they cannot be used as a single large block of memory with completely consistent bandwidth and latency. To turn this capacity into effective computing power, it still relies on data placement, migration, caching, communication libraries, and scheduling software.
Every time the scale steps up, the cost follows suit; cross-cabinet cabling, switching hierarchies, power density, liquid cooling, fault domains, and scheduling complexity all increase. Public information has already proven two things: Huawei can deliver a 384-card system and has completed a real 1,024-card machine demonstration. What remains undisclosed are three other things: the total power consumption of this 1,024-card demo machine, the actual transaction cost, and the effective task output across different models and long-term operations. A thousand-card system is no longer just a roadmap, but whether every workload is worth being hosted on a thousand-card strongly interconnected domain remains unanswered.
Beyond Huawei, domestic SuperNodes are forming product portfolios at different scales. Metax Technology's publicly announced Xijing S600 adopts a single-cabinet 64-card fully interconnected design and supports scaling to a 10,000-card cluster; Kunlunxin has landed 32/64-card products and released 256/512-card SuperNode technology [11][12]. Moore Threads has released a 128-card high-density SuperNode reference design; the Guangyue solution involving Biren Technology has landed a 128-card commercial version with optical interconnects; Enflame disclosed its 32/64-card product plans; and Hygon is entering from a CPU + DCU heterogeneous platform [13][14][15][16]. The maturity of these numbers varies: 64/128-card systems already have official products, commercial versions, or reference designs; 256/512-card systems mainly remain at the stage of technology release or architecture planning; and for 1,024 cards, there is currently at least a public demonstration of a real machine by Huawei. Domestic SuperNodes do not equal Huawei, nor do they mean that all tiers have been mass-produced.
NVIDIA: Platform Vendors Turn the Full Rack into a Commodity First
NVIDIA first turned the rack-scale system into a directly purchasable commodity. The GB300 NVL72 packs 72 Blackwell Ultra GPUs, 36 Grace CPUs, the NVLink switching system, power supply, and liquid cooling into a single rack; official specifications provide 130 TB/s of rack-scale NVLink total bandwidth and 37 TB of fast memory, with the product page marked "Available Now" [2].
Figure 5 | The GB300 NVL72 packages 36 Grace + 2 GPU compute modules, NVLink switching, power supply, liquid cooling, and management into a single purchasable full rack.
The benchmarks established by the GB300 NVL72 have two layers. One is scale: the most frequent GPU communications remain within the NVLink domain inside the rack. The other is the delivery model: challenges such as hardware-software co-design, power supply, liquid cooling, and operations and maintenance are resolved by NVIDIA before leaving the factory; what the customer buys is a full-rack product that can be replicated and deployed. Outside the rack, the system still needs to connect to InfiniBand or Ethernet to form a larger cluster.
The next step on the roadmap is the Vera Rubin Ultra NVL576, which plans to incorporate 576 GPUs into the same NVLink domain. It is currently still in the subsequent product roadmap and prototype validation stage, representing a product in a different state from the already supplied GB300 NVL72 [8].
AMD: Challenging Vertical Integration with Openness
AMD followed up with the 72-GPU full-rack form factor but did not copy NVIDIA's vertical closed loop. Helios consists of 72 MI455X GPUs, EPYC CPUs, and Pensando components; the official blueprint provides 260 TB/s of rack-scale scale-up aggregated bandwidth and 31 TB of HBM4. AMD explicitly defines it as an open reference design and does not directly sell the full rack itself; partner systems based on Helios are expected to begin large-scale deployment in the second half of 2026 [3].
Figure 6 | Helios consists of 18 4-GPU compute trays forming a 72-GPU rack; 4 Scale-up Cartridges form a UALoE multi-plane switching network, supporting 72-GPU all-to-all connectivity; outside the rack, it continues to scale via Pensando Vulcano 800 AI NICs.
In terms of card count, the two companies are tied, both with 72 GPUs per rack; the difference lies in who can turn the blueprint into a stably delivered product. NVIDIA trades vertical integration for certainty and delivery efficiency, while AMD trades open standards for supplier choice. The UALink standard supports up to 1,024 accelerators, which is merely the capability boundary of the protocol and cannot be taken as proof that Helios has already delivered a 1,024-card system [4].
Openness does not automatically eliminate the difficulty of systems engineering. What AMD needs to prove next is whether multiple partners can follow the same blueprint to produce stable, easily deployable, and consistently performing full-rack systems.
Google: Redesigning Topologies Based on Workloads Within the Cloud
Google's products remain within its own cloud. It does not need to sell generic racks to external customers; it can start from its own models, XLA compiler software, and cloud scheduling to design chips and networks in reverse. The question it asks is also different from the previous three: should pre-training, post-training, and inference share the same topology?
Let us first look at how the two chips are networked. The TPU 8t is aimed at pre-training and adopts a 3D Torus topology; the TPU 8i is aimed at post-training, sampling, and inference, and adopts a Boardfly hierarchical topology. In the TPU 8i, 4 TPUs first form a ring-shaped Building Block (BB), 8 BB boards then form a fully connected Group via copper cables, and 36 Groups are connected into a Pod via Optical Circuit Switches (OCS), with up to 1,024 chips active at most [9].
In Google's disclosed examples of the same scale, between the two most distant chips, Boardfly goes through a maximum of 7 hops, while 3D Torus goes through a maximum of 16 hops; Google also claims that latency for communication-intensive workloads is improved by up to 50%. These figures are all based on Google's own claims, and both TPU 8t and 8i are currently marked "Coming Soon," so they cannot be treated as delivered horizontal test results [9][10].
Figure 7 | The TPU 8i Boardfly scales from a 4-TPU ring BB to a Group of 8 BB boards, and then connects 36 Groups via OCS.
Google has given the industry a reminder: a strongly interconnected domain is not necessarily the bigger, the better. Pre-training values sustained throughput more, while MoE inference cares more about all-to-all data exchange across multiple cards, hop counts, and tail latency; different workloads may require domains of different sizes and different topologies.
Four Roadmaps, Addressing the Same System Challenge
Placing the four companies back on the same main industry timeline: NVIDIA first turned full-rack delivery into a commercial benchmark; AMD follows the same product form factor, using an open ecosystem to challenge vertical integration; Huawei pushes the strongly interconnected domain to multiple cabinets, with 384 cards already deployed at scale and 1,024 cards demonstrated on a real machine; and Google redesigns intra-domain communication based on workloads. There is no clear generational relationship among the four companies; the real differences lie in how large the strong interconnection is made, which system capabilities are incorporated into the product, and who ultimately completes the integration and delivery.
The winner will not be determined solely by who connects the most cards. Every card count must pass three tests: can the newly added chips be translated into newly added task output; can the system run stably over the long term under faults and workload fluctuations; and can the entire equipment be replicated and deployed at power and costs that customers can afford.
From the already supplied 72-card full rack, to the 576-card strong domain on the roadmap, to the already demonstrated 1,024-card real machine, these numbers correspond to different product stages and cannot be directly ranked into a single performance leaderboard. The change they collectively point to is: AI chip competition has moved beyond single-card specifications and entered the systems engineering stage. What ultimately prices the system is Goodput, that is, the actual effective task volume completed after the system runs stably over the long term.
Official Materials: (Scroll up and down to view):
[1] Peng Cheng Laboratory: "Promoting a New Paradigm for AI Infrastructure Construction — Jointly Release the 'SuperNode Definition and Practice White Paper' with the Global Computing Alliance" https://pcl.ac.cn/html/943/2026-07-20/content-4726.html
[2] NVIDIA: NVIDIA GB300 NVL72 https://www.nvidia.com/en-us/data-center/gb300-nvl72/
[3] AMD: AMD Helios Rackscale Solution https://www.amd.com/en/products/rackscale-solutions/helios.html
[4] UALink Consortium: FAQ https://ualinkconsortium.org/faq/
[5] Huawei: "Ascend 950 SuperNode Real Machine Debuts at WAIC 2026" https://www.huawei.com/cn/news/2026/7/atlas-950-superpod
[6] Ascend Community: Atlas 950 SuperPoD Product Specifications Page https://www.hiascend.com/en/hardware/cluster
[7] Huawei: "Leading the New Paradigm of AI Infrastructure with Pioneering SuperNode Interconnect Technology" https://www.huawei.com/cn/news/2025/9/hc-xu-keynote-speech
[8] NVIDIA: NVIDIA Vera Rubin POD: Seven Chips, Five Rack-Scale Systems, One AI Supercomputer https://developer.nvidia.com/blog/?p=113993
[9] Google Cloud: Inside the eighth-generation TPU: An architecture deep dive https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-dive
[10] Google Cloud: Tensor Processing Units Product and Availability Status https://cloud.google.com/tpu
[11] Metax Technology: "From SuperNodes to AI4S, Metax Technology Delivers a Full-Stack Computing Answer at WAIC 2026" https://www.metax-tech.com/ndetail/12499.html
[12] Kunlunxin: Company Introduction and Development History https://www.kunlunxin.com/company-profile
[13] Moore Threads: "Jointly Released 128-Card High-Density SuperNode Reference Design" https://www.mthreads.com/news/285
[14] Biren Technology: "Domestic Optical Interconnect and Optical Switching SuperNode 'Guangyue 128-Card Commercial Version' Officially Lands" https://sgc-prod.birentech.com/news/h5vjj6lsw4n5za2yw6ayyv1e/
[15] Shanghai Stock Exchange: Enflame Technology "Prospectus for Initial Public Offering of Shares and Listing on the STAR Market (Registration Draft)" https://static.sse.com.cn/stock/disclosure/announcement/c/202606/002175_20260618_55YX.pdf
[16] Hygon Information: Hygon No. 3 CPU and Hygon Deep Computing DCU Heterogeneous Computing Platform https://www.hygon.cn/news?newsid=102