Author: Zihao
This year, AI glasses have officially entered a cycle of scaled-up mass production, with strong industry growth momentum. According to IDC data, in the first quarter of 2026, the global smart glasses market achieved a year-on-year growth rate of up to 130.1%, with the Chinese market ranking third globally with a growth rate of 23.5%. It is estimated that global smart glasses shipments will reach 23.687 million units this year.
While market enthusiasm continues to rise, the overall product experience in the industry generally suffers from critical flaws. Obvious heating, short battery life, delays in visual recognition and real-time translation, and bulky overall design have become core pain points restricting user retention and industry advancement. From the perspective of the underlying industrial logic, the core problem stems from an immature dedicated chip system.
01 Three Critical Flaws Drag Down Terminal Experience
In the early stages of the AI glasses industry, the supply chain had not yet formed a mature dedicated chip system. To quickly seize the market and lower the threshold for hardware R&D, a large number of small and medium-sized OEMs directly adopted mid-range smartphone SoCs for simple tailoring and adaptation. After merely deleting some redundant modules such as basebands and high-definition video encoding, they directly embedded them into the narrow temples to complete hardware adaptation.
However, the core design logic of smartphone chips revolves around the large screen, large-capacity battery, and built-in heat dissipation space of smartphones. This contradicts the special usage environment of AI glasses, which features a narrow body, passive heat dissipation, a 200–300 mAh micro battery, and close-to-body wearing. It is difficult to achieve adaptation through simple software optimization or hardware fine-tuning, directly giving rise to three terminal experience defects, which have become common pain points for mass-produced products in the industry.
First, there is obvious heating under high-load working conditions, which destroys wearing comfort. When the smartphone SoC runs high-load tasks such as local large model inference, real-time visual recognition, and continuous AR screen rendering, the overall power consumption will instantly surge to the watt level. However, the temple structure of all-in-one AI glasses is extremely simple, without any active heat dissipation structures such as fans or vapor chambers. It relies solely on the plastic shell for passive heat conduction, making it impossible for the heat in the space to dissipate quickly.
The first-generation AI glasses equipped with tailored smartphone SoCs, when running continuously under high load for 30 minutes, generally see the hot spots in the skin-contact areas of the temples exceed 48–52°C. This is far beyond the 39°C comfort threshold for wearables; temperatures exceeding 43°C can cause noticeable burning and scalding sensations. Even for daily intermittent use, its no-load standby power consumption is much higher than that of professional wearable chips.
Second, the operational delay of core AI functions is too high. The core product competitiveness of AI glasses is concentrated in intelligent interactive functions such as real-time multilingual translation, first-person perspective object recognition, gesture and eye tracking, and spatial SLAM modeling. These functions have extremely high requirements for the computing power response speed of the chip, requiring the NPU to have millisecond-level real-time inference capabilities exclusive to wearables.
However, the NPU architecture built into general-purpose smartphone SoCs is mainly optimized for short-term computing power needs such as static image processing and short video AI effects on smartphones, and is not adapted to the normalized working scenarios of AI glasses, such as continuous streaming image acquisition and parallel inference of voice and text. After frequency reduction operation under the strict power consumption and space constraints of the temples, the delay of local translation and visual recognition of the device will exceed hundreds of milliseconds. Screen ghosting, delayed translation subtitles, and lagging object recognition have become common problems in mass-produced models, rendering the core intelligent functions of the products useless and unable to meet users' needs for real-time interaction.
Finally, the overall battery life is short, unable to support all-day wearing needs. Currently, the battery capacity of mainstream all-in-one screen-equipped AI glasses is only 150–300 mAh, with limited energy storage. Meanwhile, the no-load standby power consumption and peak operating power consumption of smartphone SoCs are both high. In conventional scenarios where voice wake-up, camera standby, and display module always-on are enabled simultaneously, a single full charge can only maintain 2–4 hours of battery life. However, the market requires AI glasses to meet the needs of intermittent use in all scenarios such as commuting, office work, travel, and sports. A short battery life of a few hours means users need to carry a charging case for frequent recharging, which weakens the core product advantage of the portability of smart glasses.
If manufacturers try to improve battery life by expanding the battery capacity, it will directly increase the overall weight. Under the current general-purpose chip solutions, the overall weight of most products exceeds 50g. Long-term wearing will cause obvious pressure and heaviness on the bridge of the nose and the sides of the ears. This is also a direct manifestation of the industry-recognized "impossible trinity" of computing power, thinness, and battery life. To achieve a qualitative change in the product experience of AI glasses and promote the industry's upgrade from quantity to quality, it is imperative to comprehensively break through the core technical thresholds of four types of dedicated supporting chips.
02 Five Types of Core Chips Each Face Technical Breakthrough Barriers
The whole machine system of AI glasses is a highly integrated micro smart hardware, driven collaboratively by the main control SoC, ISP (Image Signal Processor) and CMOS image sensors, display driver chips, PMIC (Power Management IC), and memory chips. The five types of chips perform their respective duties, determining the computing power limit, imaging effect, display experience, battery life, and body size of the whole machine respectively. However, each type of chip has different technical barriers that need to be tackled and broken through one by one in the supply chain.
As the computing core of the device, the main control SoC chip integrates core functions such as computing power processing, image imaging, wireless communication, and system management. It directly determines the intelligent interaction capability, operational delay, and overall power consumption performance of the device, and faces the most complex challenges.
First, there is a core contradiction between computing power and power consumption. Local AI computing, high-definition image processing, and real-time rendering require high computing power support, but high computing power is easy to cause problems such as excessive power consumption, body heating, and shortened battery life. From the data perspective, running local multimodal large models now requires at least 4–6 TOPS, with required computing power growing tenfold. When running synchronously under high load, the chip power consumption can surge to around 300mW, consuming 60% of the battery in just one hour of intensive use. At the same time, spatial interaction requires screen delay to be lower than 20 milliseconds, while low computing power solutions generally have a delay of over 50ms. It is difficult to balance computing power, power consumption, size, and delay simultaneously, which is also the most core SoC technical pain point in the current industry. Second, the device integration requirement is extremely high. Traditional discrete chip solutions are too large in volume to adapt to the lightweight design of the glasses body. At the same time, concurrent operation of multiple tasks is prone to scheduling lag and interaction delay. Voice recognition, image noise reduction, and wireless transmission stability in complex environments are insufficient, greatly affecting the user experience.
The current mainstream solution is to launch SoCs with higher integration, providing stable computing power without occupying more space. Qualcomm's AR1 Gen1 series SoC is a benchmark solution for high-end AR glasses, integrating a dedicated NPU, ISP image processor, and high-speed communication modules. It supports on-device AI large model computing and high-definition optical engine rendering, with mature computing power scheduling and strong stability. It is widely used in Meta Ray-Ban and high-end AR wearable devices, balancing the needs of high-performance computing and low-latency interaction. Domestic SoC manufacturers are rapidly iterating and breaking through, focusing on high computing power energy efficiency ratio and high cost-effectiveness. Manufacturers such as Rockchip, Ankai Microelectronics, CoolChip, Bestechnic, UNISOC, and Allwinner have targeted the launch of wearable-dedicated SoC chips, optimizing image processing and AI lightweight computing power to adapt to basic functions such as daily shooting, voice interaction, and real-time screen casting.
The ISP (Image Signal Processor) and CMOS image sensors are the core partners of the visual perception system of AI glasses, responsible for real-scene acquisition, image quality optimization, image noise reduction, and AI visual input. They directly determine the accuracy and effect of the device's photo imaging, spatial recognition, and environmental perception.
Also constrained by the insufficient space of the glasses body, it is impossible to equip large-size sensors, resulting in insufficient light intake. In low-light environments, the screen has many noise points and poor clarity. At the same time, the device has variable wearing postures and frequent mobile shooting, which is easy to produce motion ghosting and screen shaking problems.
The high-end AI glasses image supply chain has long been dominated by international head manufacturers, with high technical barriers. Sony and Samsung, with their advantages in high-quality CMOS sensor processes, possess core capabilities such as high photosensitivity, high dynamic range, and ultra-low dark light noise points. They have mature pixel tuning and accurate color reproduction. Moreover, their products are natively adapted to wide-angle wearable lenses, achieving high-speed imaging while keeping the power consumption of a single camera under 120mW. They adapt to the spatial positioning and high-definition shooting needs of high-end AR glasses. In the ISP field, dedicated image processing chips from manufacturers such as Qualcomm and ADI support multi-level noise reduction, HDR dynamic brightening, and motion compensation algorithms. They can quickly correct the screen distortion captured by wearable devices, greatly improving the imaging stability of dynamic scenes.
As for domestic manufacturers, OmniVision, SmartSens, and GalaxyCore have targeted the launch of wearable-dedicated miniaturized CMOS image sensors, optimizing photosensitive performance while reducing chip size to adapt to the lightweight module design of glasses.
The display driver chip is the core component of screen-equipped AI glasses, and it is also the most scarce and technically contradictory chip category in the current supply chain. It directly determines screen clarity, color performance, screen delay, and overall power consumption, and is the key to improving the experience of AR see-through, real-time screen casting, and AI graphic display.
Currently, AI glasses are generally equipped with Micro-OLED, LCoS, and Micro LED micro displays. Limited by the lightweight design of the devices, display driver chips face multiple industry pain points. On the one hand, micro displays have high pixel density and extremely small sizes. Traditional driver chips are prone to problems such as screen ghosting, uneven color, and low-brightness flickering, resulting in insufficient display clarity in outdoor strong light scenarios. On the other hand, high refresh rate and high color gamut driving will greatly increase power consumption, easily causing the overall battery life to shrink, making it hard to balance high-definition display and low power consumption requirements. At the same time, the narrow temple space has strict requirements for chip miniaturization and low EMI interference. When multiple modules work collaboratively, display delay and screen shaking are easy to occur, affecting the visual experience of wearing.
Taiwanese manufacturers such as Sitronix and Realtek have profound technical accumulation. Their driver chips have high color accuracy, low delay, and adaptive brightness adjustment capabilities, which can adapt to mainstream optical engines such as LCoS and Micro-OLED, effectively solving the problems of flickering and color distortion. They are widely used in high-end AR glasses models from Meta, Huawei, etc. Vusion Tek has deeply cultivated the micro-display driving field, optimizing the architecture for the lightweight and low-power consumption needs of AI glasses, adapting to various micro displays, and quickly penetrating the domestic market with high cost-effectiveness solutions.
As the central hub for overall power consumption scheduling, the PMIC (Power Management IC) coordinates device charging and discharging and full-link power supply regulation. The temples of AI glasses cannot be equipped with large-capacity batteries, and the battery is the heaviest part of the entire product. Most AI glasses adopt a dual-battery split power supply structure in the left and right temples to balance the weight, but this also easily leads to problems such as unbalanced charging and discharging of the dual batteries and inconsistent voltage differences, reducing battery utilization and overall battery life.
ADI's solution is to launch an integrated PMIC chip, which combines ultra-low static power consumption, high-precision power measurement, and a single-inductor multiple-output architecture. It can simplify peripheral devices and adapt to the miniaturization design needs of flagship models such as Meta Ray-Ban, effectively alleviating the problem of limited space. Power management series chips from TI, NXP, and Qorvo support multi-rail voltage regulation, dynamic load adaptation, and hierarchical sleep control, which can match the dynamic computing power fluctuations of on-device AI chips and balance performance and power consumption. Qualcomm's dedicated PMIC is deeply adapted to its AR wearable platform, accurately coordinating the power timing of the whole machine, and is the core power solution for high-performance computing AI glasses. SouthCHIP's dual-battery balancing chip specifically solves the industry pain point of uneven charging and discharging of dual-temple batteries, effectively improving the overall battery life. SGMicro's low-noise voltage regulation and multi-channel power chips can ensure the stable operation of precision devices such as cameras and 3D perception sensors. Manufacturers such as Awinic and Halo Micro have made up for the supporting links such as peripheral power supply and auxiliary voltage regulation. This full set of power solutions are widely adopted in mainstream AI glasses from Xiaomi, RayNeo, and Alibaba Quark.
Memory chips are also critical in AI glasses, shouldering the heavy responsibility of storing and retrieving data. As the functions of AI glasses become increasingly powerful and rich, AI glasses need to process and store more data, such as high-definition videos, high-resolution images, and continuously upgraded AI models. The capacity of memory chips will continue to increase, developing from the current common 32GB to higher capacities, to ensure that the device can run various complex applications smoothly. Moreover, it accounts for a relatively high proportion in the hardware cost of AI glasses. Taking Meta's Ray-Ban smart glasses as an example, the memory chips (ROM+RAM) provided by Biwin account for about 7% of its BOM cost, second only to the main control SoC chip, with a single machine value of about $11.
ePOP, namely embedded Package on Package, achieves a high degree of integration by vertically stacking NAND Flash and LPDDR above the SoC. The biggest advantage of this technology is that it can save about 60% of the PCB (Printed Circuit Board) space, making the internal layout of AI glasses more compact and helping the device achieve a lightweight and thin design. At the same time, by reducing the number of chips and connection lines, power consumption is reduced, thereby improving the device's battery life. Relying on features such as small size, low power consumption, and high performance, this technical solution has been applied by enterprises such as Meta and Google in products like AI smart glasses and smart watches.
eMCP, namely embedded Multi-Chip Package, adopts multi-chip packaging technology to integrate eMMC and LPDDR into one package. It has a built-in NAND Flash control chip, which can reduce the computing burden of the main chip, simplify the management of large-capacity flash memory, and also save motherboard space. In some AI glasses that have certain requirements for storage capacity and performance but need to control costs, eMCP technology has been widely used. It can provide a relatively economical storage solution for the device while ensuring a certain level of performance, meeting the market demand for mid-to-low-end AI glasses.
In addition to the above chip types, AI glasses also include audio processing chips, communication chips, Bluetooth chips, and so on. In the future, if AI glasses want to truly become the most popular consumer electronic products besides mobile phones, these core chips need to be upgraded simultaneously, and none can be missing.
03 External Challenges Are Equally Thorny
The AI glasses chip track also faces two major external challenges: supply chain instability and divergence in industry architecture routes, which have become key obstacles to industrial development.
At the supply chain level, the explosive growth of the AI server industry continues to squeeze the core capacity of wafer foundry and memory chips. The capacity of low-power LPDDR and small-capacity Flash memory chips originally adapted for wearable devices has been significantly compressed. The capacity tilt of original manufacturers and the continuous rise of spot prices have led to an increase in stocking costs for AI glasses OEMs. For AI glasses, the operation of local large models, real-time screen caching, and shooting material storage are all inseparable from dedicated low-power memory chips. Capacity squeeze has put a large number of small and medium-sized OEMs in a dilemma of difficult procurement and high costs. Some niche brands have even postponed the launch of new products due to the supply interruption of memory chips, seriously restricting the overall shipment growth rate of the industry.
At the same time, the problem of insufficient capacity for micro-display driver chips is becoming increasingly prominent. LCoS driver chips with mature processes and low costs have limited display effects and cannot adapt to the needs of high-end products. Meanwhile, Micro LED driver chips with better experience have a high degree of customization, slow yield climbing, and scarce capacity. Head foundry resources are highly concentrated in overseas large manufacturers. The procurement cycle for domestic manufacturers is as long as several months. Supply interruption in the peak season and order delays have become the norm, and supply chain difficulties continue to plague the industry.
At the architecture route level, there have long been two differentiated development routes, each with its own advantages and disadvantages.
One is the single-chip highly integrated SoC route represented by Qualcomm. The chip integrates CPU general-purpose computing power, multi-channel hardware ISP imaging units, micro-display drivers, Wi-Fi/Bluetooth wireless RF, and dedicated NPU all within a single 6nm chip. The peripheral components of the whole machine can be reduced by more than 40%, and the PCB area of the temple is compressed by 25%, with a prominent lightweight effect on the body. The chip internally uniformly schedules computing power, image, and wireless power consumption, reducing collaborative scheduling loss by 30%, adapting to high-end lightweight screen-equipped AI glasses with batteries within 300mAh. However, the R&D investment for tape-out of a fully integrated SoC exceeds hundreds of millions of yuan, and the terminal procurement cost of a single chip is $45–$60. The pricing is expensive, which small and medium-sized brands and entry-level models cannot afford, making it difficult to penetrate the mass consumer market below 1,000 yuan.
The other is the multi-chip heterogeneous splitting solution from Rockchip and Bestechnic, adopting a combination mode of "basic main control chip + external independent ISP/display/wireless co-processing chips". Manufacturers can selectively choose supporting chips for image, display, and audio according to product function needs. The hardware procurement cost of a single set of solutions is only $10–$20, and the product iteration and adaptation flexibility is extremely strong, making it the mainstream choice for entry-level affordable AI glasses. However, multi-chip stacking will occupy a large amount of internal space in the temple, and the overall weight is generally 10–18g higher than that of the integrated solution. When multiple chips run synchronously, power consumption superimposes on each other. In high-load shooting + spatial perception scenarios, the steady-state power consumption of the whole machine increases by about 200mW.
The two routes have their own advantages and disadvantages. Downstream manufacturers choose independently according to their needs, while upstream chip enterprises have scattered R&D directions. The industry cannot concentrate resources to tackle core technologies, and the mass production cost of dedicated chips remains high for a long time, delaying the speed of industrial maturity. All technical and supply chain issues ultimately converge on the "impossible trinity" contradiction at the bottom of the industry, which is also the most difficult core hurdle to cross in the AI glasses chip industry.
Currently, the AI glasses industry is shifting from scaled-up mass production to experience upgrade. The technical maturity and supply stability of the underlying chip supply chain will directly determine the long-term development speed of the industry.