AI Agents Revitalize CPU Value: RISC-V’s Opportunities and Challenges in Data Centers

As AI agents become deeply integrated into frontline business operations, RISC-V is penetrating data centers at an unprecedented pace. Since the beginning of this year, leading domestic RISC-V enterprises have continued to achieve breakthroughs in server-grade CPU cores, processor cores for cloud-based agents, data center management control units, and thousand-card clusters, providing a more flexible and efficient computing paradigm for AI data centers in the agent era. On the international front, NVIDIA has invested in SiFive and introduced NVLink into RISC-V systems to break the limitations of traditional CPUs on AI performance scaling. In the era of AI agents, what entry opportunities and room for development does RISC-V have in data center scenarios, and what new requirements and challenges does it face?

As the focus of AI competition shifts from large models to AI agents, the computing architecture of data centers is undergoing changes.

In the era of large models, the GPU is the core of data center computing. According to a research report by Futurum Intelligence, in 2022, CPUs and XPUs still accounted for the vast majority of the data center semiconductor market share. As general-purpose large models like ChatGPT ignited computing demand, the GPU's market share surged, reaching parity with CPUs and XPUs in 2023, and rising to approximately 75% in 2025, becoming the absolute dominant force in data center computing.

However, in the era of AI agents, the CPU is gaining momentum, showing a strong trend of "returning to the table."

"In the generative AI era, whether it is a general-purpose large model or a vertical large model combined with domain knowledge, they are all 'question-and-answer' AI, receiving prompts from users and outputting tokens after reasoning and computation. The essence of an AI agent is to closely integrate reasoning with business operations, enabling AI to 'get things done.' It is 'execution-oriented' AI, which will drive the computing paradigm of data centers to shift from 'GPU-centric compute-intensive' to 'CPU-centric control-intensive and I/O-intensive'," Li Huaqing, Co-founder and Vice President of Shanghai Lingzhi Ruixin, told China Electronics News.

Specifically, in the process of an AI agent decomposing and executing tasks, the most time-consuming parts are external tool invocation, business logic execution, and data interaction among various modules and control flows, and such workflows are borne by the CPU.

"AI agents make the CPU the value core of the data center once again, but its role is no longer the computing center, but the chief system dispatcher," Xu Tao, Founder and CEO of StarFive, pointed out to China Electronics News. "AI agents need to perform a series of complex system-level operations such as task decomposition, tool invocation, database queries, permission verification, and result validation, which are precisely the strengths of the CPU."

The shift in the CPU's positioning and its rising proportion in configuration ratios mean that the computing model of data centers is no longer confined to the single logic of "GPU-only," which also brings incremental space for RISC-V.

From the perspective of product layout, RISC-V has become the "third pole" in the CPU field alongside x86 and Arm, gaining high industry recognition. Since 2026, the domestic RISC-V CPU industry chain has achieved a series of breakthroughs in data centers. Alibaba DAMO Academy's flagship CPU XuanTie C950 has broken the 70-point mark in the Specint2006 benchmark test, setting a new global RISC-V performance record. The Institute of Computing Technology of the Chinese Academy of Sciences and the Beijing Academy of Open-source Chips have jointly created the "Xiangshan" open-source high-performance RISC-V general-purpose computing system solution. Its "Kunminghu" processor core has achieved a measured SPEC CPU2006 score of 16.5 points/GHz. Paired with "Wenyuhe," the world's first open-source on-chip interconnect network for data centers, it provides an open-source common foundation for the advanced computing ecosystem. Lingzhi Ruixin has launched the world's first dynamic 4-thread server-grade RISC-V CPU core P100, with a single-core SPEC CPU2006 performance exceeding 20/GHz. SpacemiT's third-generation high-performance RISC-V processor core X200 has completed R&D, featuring targeted optimizations for cloud-based agents and flagship terminal agent applications.

From the perspective of design philosophy, RISC-V's natural advantages such as modular design, strong scalability, and high programmability bring a more efficient and flexible design concept to AI chips, and also better align with the long-tail business needs generated by AI agents.

"As the forms and platforms of AI agents multiply, a single chip architecture is difficult to efficiently support various agents and the complex long-tail businesses generated by AI. Optimization must be combined with specific workloads and business characteristics. This is difficult to achieve for traditional instruction set architectures because their instruction sets are complete systems, and instructions cannot be selectively adopted. In contrast, RISC-V adopts a modular design concept, which allows for on-demand instruction selection and the addition of custom instructions, realizing 'workload-defined chips' and significantly improving computing efficiency and energy efficiency, which is highly attractive to AI agents," Li Huaqing stated.

From the perspective of system construction, RISC-V can bring a series of system-level advantages to data centers. Xu Tao pointed out that the advantages of RISC-V in data centers cannot be judged solely by technical indicators, but must be understood from a system perspective. Taking the management plane (control unit) of a data center as an example, what is needed is not an extremely high-performance large core, but a "sufficiently strong" core, coupled with a complete software stack, security mechanisms, and system solutions. RISC-V can quickly meet changing needs at this level, such as security requirements, scheduling requirements, and firmware and software iteration requirements.

"The core advantage of RISC-V in data centers can be summarized as the system-level controllability and customizability brought by its openness. Compared with traditional instruction set architectures, RISC-V is easier to customize according to customer wishes and can truly be implemented. The essence of this 'controllability' is the ability to accurately grasp and quickly realize customer needs," Xu Tao said.

"Being Used" Does Not Mean "Being Seen"; Entry Points Must Balance Value and Implementation

If viewed solely from the perspective of "being used," RISC-V already has a considerable shipment volume in the data center field. NVIDIA alone uses over 1 billion RISC-V cores annually in its AI chips.

However, this relatively "invisible" application cannot be equated with the large-scale application of RISC-V in data centers. Li Huaqing pointed out to reporters that the application of RISC-V cores in NVIDIA's AI chips is more like "screws on an aircraft carrier," meaning it has entered a high-value field in the form of low-end products.

So, if judged by standards such as "explicit," "critical," and "more core value," what are the currently implementable entry points for RISC-V in high-performance data centers?

At the chip level, interviewed companies, combining their own observations and practices, focus on two types of products.

The first is chips for new workloads such as AI. Wang Deke, Vice President of SiMa.ai, told reporters that as an emerging instruction set architecture, RISC-V does not need to be backward compatible with older versions of instructions like traditional x86 or Arm architectures. At the same time, as an open-source instruction set architecture, RISC-V can promptly formulate vector extension instructions and matrix extension instructions that meet requirements based on the evolution of AI, and achieve ultimate optimization in terms of performance, power, and area (PPA). In addition, AI chips relying on the RISC-V open-source ecosystem can form a good positive feedback loop in subsequent iterative optimizations. Reporters learned that in March this year, China Mobile Tibet Branch’s thousand-card RISC-V computing cluster was successfully delivered and officially put into operation in Lhasa. This thousand-card cluster was built on SiMa.ai's self-developed STCP950L NPU computing card, and during the trial operation, it flawlessly supported the deployment of models ranging from 7 billion to 671 billion parameters.

The second is chips related to the data center "management plane." Xu Tao believes that the best path for RISC-V to enter high-performance data centers is the "management plane," such as BMCs (Baseboard Management Controllers), DPUs (Data Processing Units), and memory managers. Taking the BMC as an example, as data center scales continue to expand and functional modules become increasingly complex, the coordination among various components urgently requires an independent, standardized, and controllable data center management and control unit, and the BMC based on the RISC-V architecture perfectly meets this need.

"Although the management plane ecosystem is complex, it is relatively controllable and suitable for RISC-V's current level of capability maturity. Entering from the management plane is a pragmatic path for RISC-V to land in data centers," Xu Tao said. It is reported that in November 2025, StarFive released its first data center management chip based on the RISC-V architecture, "Shizi-Shanxin", achieving the first large-scale commercial implementation of RISC-V in the data center field.

At the business and application level, Li Huaqing believes that compared to open general-purpose computing platforms, vertical businesses such as data center storage clusters and database clusters will be easier entry points for RISC-V to implement.

"The ecosystem of RISC-V can be viewed from two levels: the basic ecosystem and the commercial ecosystem. Currently, RISC-V already has a good basic ecosystem, capable of supporting more and more operating systems, compilers, and system basic libraries; however, in terms of the commercial ecosystem, because RISC-V previously lacked high-performance hardware platforms, and commercial software basically runs on high-performance CPUs, the commercial ecosystem of RISC-V is relatively weak," Li Huaqing said. "The number of software applications for vertical businesses is limited and controllable. By providing services through standard interfaces, it can overcome the shortcomings of RISC-V in the commercial ecosystem."

Taking the data center storage server cluster as an example, the types of software running on the servers are relatively fixed (file storage, block storage, object storage, etc.), and the quantity is relatively controllable. After completing the configuration and optimization of these software applications, services can be provided externally through standard interfaces. In terms of business form, business logic and data storage are in a loosely coupled or decoupled state. Compared to open platforms, this application form, which is self-contained within the interface and decoupled from upper-layer business outside the interface, can better help RISC-V cope with ecosystem challenges and truly take root and land in data centers.

RISC-V CPUs Face Five New Requirements; Underlying Capabilities, Ecosystem, and Industrial Synergy All Need Improvement

Although AI agents have opened up more entry opportunities and incremental space for RISC-V, they have also put forward a series of new requirements for CPU and AI chip design, which is a topic that RISC-V IP, chip, and system design enterprises must consider.

Taking RISC-V CPUs as an example, AI agents mainly put forward five types of requirements for CPU design.

The first is concurrency capability. Li Huaqing stated that the completion of future enterprise-level tasks often requires the joint collaboration of multiple AI agents, involving a large amount of concurrency of various types of tasks such as data preprocessing and post-processing, reasoning computation, tool invocation, and data interaction, which puts forward higher requirements for the concurrency capability of the CPU. The dynamic 4-thread technology of Lingzhi Ruixin's P100 is precisely designed to meet this need.

The second is a significant increase in memory capacity. Xu Tao pointed out that the CPU needs main memory with a capacity far exceeding that of GPU HBM to support the state of complex tasks and maintain context management.

The third is low latency and high bandwidth. As the chief system dispatcher directly facing end-users, the CPU's response speed must be faster than the human perception threshold, with no obvious waiting time.

The fourth is that the co-design of CPUs and AI chips will become more common. Wang Deke mentioned that future data center computing systems with AI-native design will move towards an architecture where CPUs and AI chips are balanced with each other, to support the continuous high loads, massive storage, data movement, and low-latency, high-concurrency network requirements needed by AI agent businesses.

The fifth is security and authorization mechanisms. Xu Tao stated that the autonomous behavior of AI agents brings new security challenges. For example, an AI agent might misread an email and execute a purchase operation on behalf of the user. This is not a traditional anti-attack issue, but a "security agreement" issue between the user and the AI agent, requiring chip-level and system-level permission control and behavior audit mechanisms.

In addition, for RISC-V to truly land in data centers, it cannot just focus on performance benchmarks, but must think about how to make RISC-V usable and used well. Xu Tao pointed out that RISC-V must prioritize making up for its underlying core capabilities.

First is the standardization of server platforms. RISC-V International is promoting server platform specifications such as RVA23 (RISC-V Server Platform Specification), which is the foundation for the entire industry chain's synergy.

Second is virtualization capability. Virtualization is a core rigid demand for data centers, and related specifications still need to complete real-scenario verification and performance tuning.

Third is the memory system. RISC-V needs to improve its support for high-performance, large-capacity, and high-reliability memory systems to support high-computing and large-memory business workloads.

Fourth is the RAS mechanism. Reliability, Availability, and Serviceability are the bottom lines for server commercial access and also the core prerequisites for customer procurement. Currently, RISC-V's related server-level RAS mechanisms still need to be improved.

Fifth is firmware security. Firmware security is the core guarantee for the stable and trusted operation of servers. Currently, the supporting systems for RISC-V firmware security architecture and secure boot are not yet mature.

It is also worth noting that, facing the latest needs of AI agents, RISC-V must advance with the times in standard development and ecosystem adaptation. Wang Deke stated that in terms of AI, the standardization of the matrix instruction set needs to be promoted as soon as possible; in terms of peripherals, it needs to adapt to the latest DDR, PCIe, and CXL standards; in terms of the ecosystem, the implementation of the RVA23 specification should be further promoted to ensure the compatibility of the software ecosystem.

At the level of industrial collaboration, a phased rollout mechanism needs to be established to enhance mutual trust and cooperation between the upstream and downstream of the industry chain. Li Huaqing mentioned that high-performance products of RISC-V for data centers have high R&D and tape-out costs. If they are only provided to the developer community, it will be difficult to realize their commercial value. However, for downstream customers, high-performance products will be used to carry important businesses, and the cost of trial and error is too high. "This requires the upstream and downstream of the industry chain to jointly explore a phased rollout mechanism, such as starting with some applications that can be relatively decoupled from the business and have a small impact range, and gradually enhancing user confidence," Li Huaqing said.

Author | Zhang Xinyi Editor | Qiu Jiangyong Art Editor | Maria Supervisor | Zhao Chen