01. Company Profile
Shanghai UniVista Industrial Software Group Co., Ltd. (hereinafter referred to as "Univista"), founded in 2020 and headquartered in Shanghai, is a platform-based enterprise in the field of domestic digital chip EDA tools and high-speed interface IP. Taking EDA and IP as its primary breakthrough directions, the company's products cover digital chip verification, digital back-end design, system-level EDA, and high-speed interface IP, providing semiconductor enterprises with pre-silicon and post-silicon tools and IP solutions.
The density of technological investment determines the upper limit of an EDA company. As of August 31, 2026, Univista has accumulated over 400 valid intellectual property rights, covering invention patents, utility model patents, and software copyrights. The group has approximately 1,300 employees, and the number of international EDA experts holds an advantage among domestic peers. In the innovation team of Univista, many members have 15 to 20 years of experience in the EDA field, possessing profound technical backgrounds and superb professional capabilities.
Relying on its independent R&D capabilities, the company has been recognized as a national-level "Little Giant" enterprise specializing in new and unique fields, and a national-level high-tech enterprise. Its products have won multiple industry awards, including the "IC Innovation Award" from the China Integrated Circuit Design Innovation Alliance, the "China Core" Outstanding Supporting Service Product, and the EDA Special Award.
02. Industry Position
EDA is the fundamental tool for IC (Integrated Circuit) design, covering the entire process of design, manufacturing, and packaging and testing. According to data from the ESD Alliance under SEMI, the global EDA market size was approximately USD 15.7 billion in 2024, with a CAGR of 6.4% from 2020 to 2024. In the second quarter of 2025, the combined revenue of EDA and silicon IP reached USD 5.089 billion, a year-on-year increase of 8.6%. Based on the ESD Alliance's figure of USD 15.7 billion for the global EDA market in 2024 and WSTS's global semiconductor sales of USD 627.6 billion in the same year, the EDA segment accounts for only about 2.5% of the semiconductor industry's volume, yet it determines the design efficiency and technological upper limit of the entire industry.
The growth rate of China's EDA market is higher than the global average. According to IDC forecasts, the size of China's EDA market will grow from CNY 10.52 billion in 2024 to CNY 23.50 billion in 2029, with a CAGR of 17.4%.
In the domestic EDA camp, Univista's positioning is scarce: it is currently the only domestic EDA enterprise that can fully cover the entire process of digital chip verification, digital back-end design, and DFT (Design for Testability), while simultaneously providing high-speed interconnect IP for advanced processes and system-level tools. This horizontal coverage capability directly addresses the fragmentation shortcoming of "many point tools but lack of full-flow" in most local EDA enterprises.
According to the "2025 China Mainland EDA Enterprise Patent Strength Ranking" released by Jiwei Consulting in January 2026, Huada Jiutian ranked first with 677 patents. The number of patents and innovation strength score of Univista increased significantly year-on-year, ranking second on the list.
03. Main Products and Advantages
(I) Main Products
The product matrix of Univista unfolds along multiple product lines such as "chip-level EDA - system-level EDA - high-performance IP", accompanied by a horizontally integrated AI intelligent platform.
1. Full-process digital chip verification: Covers four forms: software simulation, hardware emulation, prototype verification, and virtual and hybrid prototypes. The software simulation side includes the next-generation digital simulator UVS+, the next-generation digital verification debug platform UVD+, and the verification efficiency management system VPS; the hardware emulation side includes the hardware emulation acceleration verification platform UVHP; the prototype verification side includes the all-scenario verification hardware system UVHS/UVHS-2 that can simultaneously cover hardware emulation and prototype verification, the single-system prototype verification platform PD-AS, and the virtual prototype platform V-Builder/vSpace. Among them, UVS+ supports mainstream standards such as Verilog, SystemVerilog, and UVM, as well as advanced functions like UPF, SystemC, mixed-signal simulation, and X-prop. It adopts a fully self-developed architecture and supports the domestic server ecosystem.
2. Digital chip implementation: Includes the 3D chip physical design tool UniVista 3DIC Designer and the domestic advanced process node convergence tool UniVista NodeClosure. 3DIC Designer is aimed at 2-die/3-die logic folding and multi-die heterogeneous stacking, supporting billion-gate level designs, and adopts a CPU+GPU heterogeneous parallel architecture; NodeClosure supplements the back-end ECO (Engineering Change Order) capabilities of domestic digital EDA, with a built-in "DRC and timing" collaborative repair engine.
3. Full-process DFT: The Tespert series covers BSCAN (Boundary Scan), MBIST (Memory Built-In Self-Test), SCAN (Scan Chain Insertion), ATPG (Automatic Test Pattern Generation), DIAG (Defect Diagnosis and Panoramic Comparative Analysis), YIELD (Yield Analysis), and IJTAG (Test Integration); AIMBIST extends the MBIST process to mass production yield analysis with AI-driven intelligent grouping and a lightweight hierarchical architecture.
4. System-level EDA: Includes the schematic design environment Archer Schematic, the PCB (Printed Circuit Board) design environment Archer PCB (with no layer limit, supporting million-level pin design scale), the collaborative design platform UVI, and the electronic system R&D management environment EDMPro, covering PCB design, package design, and 2.5D/3D advanced packaging collaborative design.
5. High-performance IP: Covers high-speed interface and memory IPs such as PCIe Gen5, UCIe, HBM3/E, DDR5, LPDDR5, Ethernet Controller, RDMA, PAXI, UEC MAC, and MPS, supporting advanced processes both domestically and internationally.
6. Digital design AI intelligent platform: UDA, UDA 2.0, UDA 3.0, as well as the EDA agent suite UniVista Verification GOAT released in September 2026 (including four expert-level agents for software simulation, verification debugging, regression test management, hardware emulation, and FPGA prototype verification) and the AI-native electronic system design platform Archer AI+.
(II) Core Advantages
1. Full-process coverage advantage: The only domestic EDA company that simultaneously covers the full process of digital chip verification, digital back-end physical design, and full-process DFT, while providing high-speed interconnect IP for advanced processes and system-level tools. Customers do not need to stitch together processes among multiple point tools, making up for the fragmentation shortcoming of domestic EDA.
2. Hardware verification capacity advantage: UVHS-2 can cascade up to 192 AMD's latest model FPGA chips, and the maximum capacity of a single UVHP system can reach 46 billion gates, supporting system-level hardware and software co-verification for high-computing-power chips.
3. Self-developed architecture and domestic ecosystem adaptation: Core tools such as UVS+ and UVD+ adopt a fully self-developed compilation and database architecture, supporting the domestic server ecosystem. In July 2026, Univista, together with Haiguang Information and Qilin Software, jointly released a fully domestic industrial design all-in-one machine solution. With the Archer series as the core design software, Haiguang processors as the computing power core, and the Kylin OS as the foundation, it achieves full-stack domestic adaptation of design tools, computing power, and operating systems.
4. Intelligent computing interconnection positioning advantage: The company's super-node interconnect IP Stack has completed SUE certification and has completed the SUE protocol docking test with Broadcom's Tomahawk Ultra switching chip. In 2024, more than 10 AI/GPU manufacturers used its intelligent computing interconnect IP and completed the networking verification of the docking switching chips. In 2025, the chip enterprises under the top three domestic Internet companies have all adopted its super-node interconnect IP.
5. First-mover advantage in AI and Agentization: In September 2026, released UDA 3.0, the first domestic agent tool based on a fully self-developed EDA architecture, specifically optimized for the chip field. During the same period, multiple products were included in the Agentic EDA agent strategy. Its GOAT suite adopts a goal-driven professional agent architecture, where engineers define task objectives, authority scope, and acceptance criteria. The agent completes analysis and execution, the EDA tools output real engineering feedback, and finally, engineers make decisions based on a traceable evidence chain.
04. Core Customer Base
The total number of customers of Univista exceeds several hundred, covering the main camp of high-end digital chip design in China.
1. Intelligent computing and AI chip enterprises: This is the customer group the company has invested in most deeply. The company has helped more than dozens of domestic intelligent computing chip customers complete the new generation of super-node interconnection solutions, with products covering the entire process from IP, networking verification to custom design. The verification scale of AI training chips is measured in billions of gates, showing the highest dependence on hardware emulation capacity and interconnect protocol verification.
2. GPU/HPC and data center chip enterprises: Most of the domestic major AI, HPC, and GPU customers have adopted Univista's products, involving chip verification, networking verification, and yield improvement.
3. Communication and 5G field customers: Design enterprises for 5G communication and communication network equipment chips. Their large-scale SoC (System on Chip) verification has prominent requirements for simulation performance and the efficiency of the regression test management platform VPS.
4. Automotive electronics and intelligent driving customers: AUTO, AD/ADAS intelligent driving chip suppliers. Full-process DFT tools have been deployed in batches in leading enterprises of automotive electronics and advanced process chips. Test diagnosis and mass production yield analysis are the core demands of customers in this track.
5. Consumer electronics, MCU, and industrial IoT customers: Covering application fields such as MCU, consumer electronics, video and image processing, smartphones, and IoT/IIoT, mainly entering through prototype verification platforms and the PHINE Design series products.
05. National R&D Layout and Service Network
Univista has built a service system of "Shanghai headquarters + multi-city R&D centers + localized technical support", making it one of the companies with the most intensive R&D layout among domestic EDA enterprises.
1. R&D layout: Headquartered in Shanghai, the Shanghai Zhangjiang Group headquarters was put into use in March 2023. R&D centers and service institutions were successively established in Beijing, Shanghai, Shenzhen, Xiamen, Chengdu, Xi'an, Wuxi, Nanjing, Changsha, and Hangzhou, forming an R&D network covering the Yangtze River Delta, Pearl River Delta, Beijing-Tianjin-Hebei, and central and western regions, enabling nearby docking with customer project teams.
2. Technical support system: The company provides on-site and remote combined technical support for domestic high-end chip projects. The technical service team has practical experience in complex large-chip projects.
3. Ecological synergy layout: Jointly established the ODCC AI Network Joint Laboratory with CAICT and Tencent, and released the ETH-X scale-up protocol networking test report; signed a strategic cooperation agreement with the Shanghai Integrated Circuit Technology and Industry Promotion Center to jointly build an integrated circuit design ecological service platform based on domestic EDA; in September 2026, jointly built the AI4EDA practical education platform with Chuangxin College to supplement industrial supply from the talent cultivation end.
4. Hardware product supporting capability: The company provides verification hardware support such as FPGA daughter cards, high-speed interface cards, memory cards, and video cards, and covers system-level services from prototype to production, including design for testability services, back-end implementation services, and networking test certification.
06. Supply Chain Services
As an industrial software enterprise, the essence of Univista's "supply chain" is the degree of independent controllability of the tool chain and the breadth of ecological adaptation.
1. Independent and controllable guarantee: Core tools adopt a fully self-developed architecture and database format, free from the constraints of overseas EDA authorization chains. During the window period in May 2025 when the supply of overseas EDA to China was restricted, the company was one of the few suppliers capable of continuing to provide full-process digital verification tools to domestic customers. This supply continuity is equivalent to risk hedging for projects that have entered the mass production ramp-up.
2. Product iteration and delivery capability: The company maintains an annual new product release rhythm, launching nearly 50 products cumulatively over five years. Since the first product UVS was released in 2021, a complete tool chain from simulation, debugging, hardware acceleration to prototype verification has been formed, so customers do not need to wait for the gap in a certain link to be filled.
3. Localized technical support and migration services: Technical teams from international EDA companies are familiar with the usage habits of mainstream tool chains and can assist customers in smoothly migrating from existing processes. Self-developed tools natively dock with international mainstream place and route tools without modifying existing script architectures, reducing the actual threshold for tool switching.
4. Domestic ecological adaptation: Tools support the domestic server ecosystem; the Archer series has completed compatibility mutual certification and deep optimization with Haiguang processors and the Galaxy Kylin operating system. Back-end tools are deeply adapted to the customized manufacturing rules and exclusive process constraints of domestic foundries, bridging the rule gap between the design end and the manufacturing end.
5. Intellectual property and compliance guarantee: As of August 31, 2026, it has accumulated over 400 valid intellectual property rights. Products have obtained qualifications such as the "IC Innovation Award" from the China Integrated Circuit Design Innovation Alliance and the "China Core" Outstanding Supporting Service Product, providing traceable supporting materials for customers in independent and controllable audits and supply chain compliance reviews.
6. Authorized agency services: As an authorized agent of Univista, Xinzhiyun has completed the introduction of the full series of digital EDA tool product lines of Univista. It provides localized services to customers such as product trial and evaluation applications, design process selection and migration plan docking, genuine authorization, and technical support response, helping customers quickly implement tools within the project cycle.
07. Company Dynamics
(I) Market Outlook
AI computing power demand is pushing EDA to a new technological highland. According to data from the China Semiconductor Industry Association, the growth rate of China's EDA market continues to lead the global average. The competition logic of intelligent computing chips has shifted from single-chip performance to system-level networking. Comparative data presented by Yang Kai, Vice President of Univista, at the ICCAD-Expo 2025 Summit Forum shows that the computing power of a single chip for China's intelligent computing chips is about 30% of that of North American products. However, the computing power after 384-card networking (FB16) can reach 300 PFLOPS, which is 1.7 times that of the North American 72-card networking solution, with a networking memory capacity of 3.6 times and a Scale-Up bandwidth of 2.1 times. System-level networking capability has therefore become the decisive factor, and networking verification and interconnect IP are precisely the core capability areas of Univista.
China's intelligent computing chips will enter a comprehensive "super-node era" in 2026. Univista will continue to invest in multiple dimensions from IP, networking verification, EDA tools to custom design and test certification, with the goal of fully supporting the explosive window of domestic intelligent computing chips.
(II) Product and Delivery Capability
1. Product iteration rhythm: Maintains an annual new product release mechanism, launching nearly 50 products cumulatively over five years. Since the first product UVS was released in 2021, a complete tool chain from software simulation, hardware acceleration to prototype verification, DFT, digital back-end, and system-level design has been formed, so customers do not need to wait for the gap in a certain link to be filled.
2. Product maturity verification: Digital verification software tools have been polished through millions of customer project use cases, and the UVS series has been successfully applied in more than 50 key chip projects. AI capabilities are directly translated into revenue in the mass production link—the full-process MBIST platform AIMBIST achieves an area reduction of over 30% through a lightweight hierarchical architecture.
3. Hardware platform delivery and deployment: A full series of hardware verification products has been built, including the PHINE Design series based on single-chip FPGA development boards, the large-scale all-scenario hardware verification system UVHS series, and the data center-level hardware emulation system UVHP series. These cover application fields such as MCU, IoT (Internet of Things), consumer electronics, video and image processing, smartphones, communication networks, AD/ADAS intelligent driving, AI intelligent computing, and HPC supercomputing, and are equipped with hardware components such as FPGA daughter cards, high-speed interface cards, memory cards, and video cards.
4. Localization delivery solution: The Archer series software has completed compatibility mutual certification and deep optimization with Haiguang processors and the Galaxy Kylin operating system (desktop and server sides), and is directly delivered to customers in the form of a fully domestic industrial design all-in-one machine.
5. Service delivery capability: Univista has approximately 1,300 employees. Multi-city R&D centers can support customer projects nearby and provide system-level services from prototype to production.
(III) Product and Technology Dynamics
In 2026, the product rhythm of Univista remains intensive. In March, the second-generation digital design AI intelligent platform UDA 2.0 was released, becoming the first domestic agent tool based on a fully self-developed EDA architecture, and the UDA 3.0 version optimized specifically for chip design was released in September. In June, Tespert SCAN and Tespert IJTAG supplemented the scan chain insertion and test integration capabilities. On September 1, the company released the next-generation EDA innovation matrix at the 2026 IDAS Design Automation Industry Summit, including the Agentic EDA agent strategic system and digital back-end physical design tools (3DIC Designer, NodeClosure). Among them, 3DIC Designer is the first domestic 3D chip physical design tool, filling the gap in domestic commercial-grade 3DIC physical design tools. AIMBIST achieves an area reduction of over 30% through a lightweight hierarchical architecture.
VIII. One-Sentence Recommendation for Univista
Univista is the only domestic EDA company that fully covers the entire process of digital chip verification, digital back-end physical design, and full-process DFT, while simultaneously providing high-speed interconnect IP for advanced processes and system-level tools. Since its establishment, it has cumulatively launched nearly 50 products, accumulated over 400 valid intellectual property rights, and served hundreds of customers. In the current context of restricted advanced processes, with the combination of "EDA + IP + system-level", it provides an independent and controllable foundation from design to tape-out for domestic AI, GPU, HPC, and automotive chips.
Content Reference Sources
1. Global EDA market size (approximately USD 15.7 billion in 2024, CAGR of 6.4% from 2020 to 2024): Data from the ESD Alliance under SEMI, cited from https://xueqiu.com/1349924180/335591523
2. Combined revenue of EDA and silicon IP in Q2 2025 reached USD 5.089 billion, a year-on-year increase of 8.6%: ESD Alliance/SEMI Electronic Design Market Data Report, cited from https://k.sina.com.cn/article_5953466483_162dab07301901gw62.html
3. China EDA market size forecast (CNY 10.52 billion in 2024 → CNY 23.50 billion in 2029, CAGR of 17.4%): IDC forecast, cited from https://www.cinn.cn/yc/2025/10-29/9k63xJm1.html
4. Global semiconductor sales of USD 627.6 billion in 2024 (the basis for calculating that EDA accounts for about 2.5% of the semiconductor industry): Data from the World Semiconductor Trade Statistics (WSTS), cited from https://guba.sina.cn/view_104291_20547.html
5. "2025 China Mainland EDA Enterprise Patent Strength Ranking": Jiwei Consulting, released in January 2026, cited from https://weibo.com/ttarticle/p/show?id=2309405250375585497109