Introduction: Kimi K3 First Hits the Compute Ceiling. Kimi K3 has pushed Chinese models to the frontier, bringing the compute bottleneck to the forefront. The next phase of domestic AI chips will not only compete on single-card parameters but also on interconnects, software, reliability, and large-scale delivery. The SuperNodes densely showcased at WAIC 2026 are the concentrated answer to this systems war.
On July 19, just three days after the release of K3, Moonshot announced the suspension of new subscriptions. This is not a product delisting; rather, request volumes far exceeded expectations, pushing service capacity close to the GPU compute limit. The speed at which users vote with their feet is faster than any benchmark score on the charts; but it also exposes another reality: supply cannot keep up with demand.
The model is indeed large and powerful. With 2.8 trillion parameters, a 1 million token context window, and a sparse MoE (Mixture of Experts) architecture (896 experts, with 16 activated per token). Artificial Analysis evaluated it on July 17, giving it a score of 57, ranking it third globally at the time, trailing behind Claude Fable 5 and GPT-5.6 Sol—the model has entered the frontier tier but has not yet reached the top.
Let's look at the scale first. K3 officially adopts MXFP4 weights and MXFP8 activations. Calculating roughly at 4 bits, the bare weights for 2.8 trillion parameters amount to about 1.4TB; adding activation values and KV Cache, VRAM usage will continue to expand. Then look at the architecture. 896 experts cannot all be stuffed into a single card; tokens need to be routed across cards to different experts, which means high-frequency cross-card communication. Kimi therefore explicitly recommends using SuperNodes with more than 64 accelerators for inference deployment. This means the inference cost of K3 is no longer determined by single-card performance, but by cluster interconnect and scheduling efficiency.
This demand is not unique to K3. On OpenRouter, an aggregation platform where developers call various models, US models accounted for about 75% of token consumption in 2025; by early June 2026, Chinese models had collectively surpassed them. Moreover, efficiency gains will bring a counterintuitive result: the cheaper a single inference becomes, the more willing enterprises are to split search, coding, and Agent workflows into more model calls, leading to an overall increase in total token consumption. Efficiency improvements lower unit costs but may exacerbate total compute pressure through demand expansion. The capacity emergency of K3 is not just a hit event, but also a microcosm of the compute rebound effect.
Interestingly, the AP's WAIC report mentioned two things simultaneously: Moonshot has a cooperative relationship with Huawei; and Huawei's Atlas 950 is a key compute exhibit at the show. These are parallel signals from the demand and supply sides, but K3's training hardware remains undisclosed, so we cannot infer that K3 uses Ascend for training or inference. What is truly worth questioning is: when models cross the trillion-parameter threshold, can domestic compute turn "benchmark scores" into continuously deliverable tokens?
Figure 1 | Scoring Method for Domestic Compute: Peak Compute is the "Horsepower Meter," System Effective Compute is the "Lap Time"
I. This Year's WAIC: The Protagonist Shifts from a Single Card to a Wall of Compute
From July 17 to 20, WAIC 2026 was held in Shanghai. Official data shows: the exhibition area exceeded 100,000 square meters, with over 1,100 enterprises bringing more than 3,000 exhibits, and over 300 global debuts. Looking at the big picture, this is a comprehensive exhibition spanning from models and chips to robots and industry applications; looking at the compute exhibition area, the most striking change is not another single card, but SuperNodes and clusters being pushed to center stage.
The display methods at the booths have changed. In previous years, manufacturers placed chips or accelerator cards in the prime spot; this year, it's one cabinet, several cabinets, or even an entire wall of compute. Huawei showcased the Atlas 950 physical system composed of 16 compute cabinets and 1,024 Ascend processors; Alibaba, Moore Threads, MetaX, ZTE, and others also made SuperNodes the protagonists. Product boundaries are expanding from chips to interconnects, servers, liquid cooling, software, and scheduling systems.
Behind the change in display is a shift in the scoring method of the compute game. Single-card peak performance remains the foundation, but it no longer equals the compute capacity customers receive. What truly determines competitiveness are five things: (1) the bandwidth and latency of Scale-up interconnects; (2) effective cluster utilization rate; (3) real model throughput; (4) fault recovery and long-term stability; (5) total cost per million tokens. Peak compute is the horsepower meter; effective compute is the lap time.
This article only discusses high compute in data centers: GPGPUs, NPUs, and ASICs for training and inference, as well as the SuperNodes built around them. Edge and endpoint chips are excluded from comparison. ZTE and Lightelligence are analyzed as a system architecture provider and an optical interconnect supplier, respectively.
Table 1 | Full Landscape of Domestic High Compute at WAIC 2026. The layered criterion is only one—whether the compute chip is self-developed; the "Compute Architecture" column indicates the chip type, and the "Role & Strategy" column only describes what the manufacturer does.
Note ① "General Accelerator Card": The five architectures are not uniform—Tianshu Zhixin, MetaX, Biren, and Moore Threads lean towards GPU/GPGPU, while Enflame's SuiSi follows the GCU (DSA) route; this table merges them under a general term.
Note ② Endpoint and edge chips are out of the scope of this article, so SOPHGO only lists its data center product BM1690.
II. If a Single Card Can't Keep Up, Turn a Bunch of Cards into a Supercomputer
Why have SuperNodes suddenly become important? First, let's see how models consume compute. Parameters, activation values, and KV Cache cannot fit into a single chip, so the model must be partitioned across multiple cards. K3's 896 experts are deployed in a distributed manner, and the router selects 16 experts for each token, generating cross-card All-to-All communication. If transmission cannot keep up, compute units will queue up waiting for data. The more cards stacked, the more severe the data congestion; no matter how high the paper FLOPS, it cannot be converted into real throughput.
The solutions split into two paths. Scale-out goes through cross-node networks, where communication must pass through NICs, switches, and navigate the software stack; Scale-up pulls dozens to thousands of accelerators into the same high-speed compute domain, collaborating with dedicated links and unified protocols. In other words, a regular cluster is like transferring files across companies, while a SuperNode is like collaborating in the same war room. Some solutions also provide unified addressing to reduce explicit data movement. Of course, the bandwidth and latency of remote memory still do not equal local HBM.
All-Reduce in training, All-to-All between experts in MoE, and the KV Cache expansion in long-context inference—these three types of workloads are all pushing interconnects to the forefront. The commonality can be summarized in one sentence: computing fast is not enough; data must be delivered in time. When advanced process nodes are constrained, system efficiency is the most realistic path for domestic chips to make up for single-point gaps.
This is not a narrative unique to China. NVIDIA's GB200 NVL72 organizes 72 GPUs into a rack-level NVLink domain, aggregating an interconnect bandwidth of 130 TB/s. The whole world is shifting from selling cards to selling systems. But the number of cards is not the scorecard: for the same 64 or 128 cards, the Scale-up domain size, topology, communication libraries, fault isolation, and measured token throughput may be completely different.
Figure 2 | The Essence of SuperNodes: Incorporating More Chips into the Same High-Bandwidth, Low-Latency Scale-up Compute Domain
III. Four Mainlines, the Same Ruler: Huawei, Alibaba, Moore Threads, and MetaX
Huawei: Rewriting the Process Gap as a Systems Problem. The Atlas 950 on-site at WAIC is a 1,024-card physical system, with peak specifications of 1 EFLOPS FP8, 2 EFLOPS FP4, a 256 TB global unified memory addressing space, and a 3-microsecond interconnect round-trip latency. The 256 TB here is the addressing space, not physical HBM, and unified addressing does not mean remote access is as fast as local access. There are two more layers above this: the 8,192-card SuperPoD is planned for launch in Q4 2026, and 64 SuperPods will be combined via Scale-out to form a SuperCluster of over 520,000 Ascend 950DT chips. The exhibition model, the single SuperNode roadmap, and the cluster represent three scales. Huawei claims that the previous generation Ascend 384 SuperNode (Atlas 900 A3) has been commercially deployed in over 750 sets—the engineering experience is there, but the customer workloads, power consumption, TCO, and long-term stability of the Atlas 950 itself still await post-launch verification.
Alibaba: Integrating Chips into the Cloud Closed Loop. Zhenwu M890, Panjiu AL128, Alibaba Cloud scheduling, Bailian model platform, and the software stack are within the same system. The advantage lies not in single-item peaks, but in the co-iteration of hardware and software: compilers, scheduling strategies, model services, and billing data can reversely optimize chip utilization. The boundaries are also clear: the AL128 has 128 chips per cabinet, and the officially disclosed full-bandwidth interconnect domain is 64 cards; Bailian has listed models like Tongyi, DeepSeek, and Kimi, but Alibaba has not disclosed one by one which underlying chip these models run on.
Moore Threads: Thinning the Network Hierarchy First. The MTT C256 uses two cabinets with 256 cards to form a single layer of Scale-up network, aiming to cut the paths and latency brought by multi-level switching. Fewer layers do not mean simpler engineering; the pressure just shifts from topology to switching chips, SerDes, wiring, and communication software. The company has successfully completed zero-to-hero training for MoE-236B, which is an internal link verification; but model performance, training cycles, and customer deployments have not been fully disclosed. Showcasing a system and achieving continuous stable training for customers are two different exam papers.
MetaX: Partitioning Workloads Beyond General GPUs. The Xijing S600 focuses on a single-cabinet 64-card full interconnect, while the Xiyun C600 adopts HBM3e and MetaXLink-E. MXMACA is highly compatible with the CUDA ecosystem at the API level; there is also the Xisuo X300 series for AI4S. Behind the three product lines is an industry trend: training looks at mixed precision and multi-card long-term stability, inference looks at concurrency and token cost, and scientific computing also requires complete floating-point precision and HPC toolchains—no single chip can eat it all. The S600 made its debut at WAIC, and the delivery scale is pending disclosure.
Table 2 | Comparison of Four SuperNodes: Parameters based on company statements, maturity based on public evidence.
Peak specifications are all announced by manufacturers; different precisions and test conditions cannot be directly compared horizontally.
The true dividing line among the four is not who writes the largest number of cards, but where the system control lies. Huawei is betting on a larger unified compute domain, Alibaba on cloud utilization and iteration closed loops, Moore Threads is exploring upwards from general GPUs to network and training systems, and MetaX uses a segmented strategy to improve scenario adaptation. The common next hurdle is turning launch parameters into reproducible throughput, stability, and token costs for customers.
Figure 3 | Public Evidence Map of the Four SuperNode Roadmaps Across Five Metrics.
Note: Color blocks indicate the visibility of public information and each company's promotional focus, not representing quantitative scores or measured conclusions.
IV. As More Cards Are Stacked, the Bottleneck Shifts from Compute to Transmission
As the Scale-up domain moves from 8 cards to 64, 128, or even thousands of cards, interconnects are no longer supporting actors. The number of links, switching layers, congestion control, and fault rerouting will jointly determine effective throughput. The most noteworthy hardware signal at this WAIC is that optical interconnects are beginning to advance from between-rack data center networks to the interior of SuperNodes and near-package locations.
Biren: Pushing Optics Next to the Chips. The BLink 2.0 route covers 16-card servers and 128-card cabinets, and plans an NPO (Near-Package Optics) architecture for 1,024 cards. Four keywords—unified memory semantics, in-network computing, congestion control, and link self-healing—correspond to two old problems: reducing the overhead of explicit copying and GPU participation in reduction, as well as congestion and fault propagation after scaling. The boundaries are clear: BR2xx and the 1,024-card NPO are still product roadmaps, with no customer deployments of the same scale yet.
Enflame and Iluvatar CoreX: Taking One Step Each on the Physical and Logical Layers. Enflame's ESL64-O uses orthogonal connections to shorten the electrical path between compute trays and switching trays, while the ESL64-C retains a cabled solution for easier deployment and maintenance; according to public disclosures, currently only one set of ESL64 prototypes has been delivered to key customers, and batch revenue has not yet been formed. Iluvatar CoreX's Tiangai 300 follows the SIMT route, optimizing at the chip and software levels for the most compute-intensive operations in current large models (Attention, MoE, and PD disaggregated inference). One reduces loss in physical topology, and the other aligns the compute architecture closely with model workloads. To truly convert interconnect bandwidth into token throughput, both layers are indispensable.
ZTE and Lightelligence: Turning Interconnects into an Independent Product Layer. ZTE's OEX uses an orthogonal, backplane-less structure to shorten SerDes paths; dOCS, in collaboration with partners like Lightelligence, connects domestic accelerators with intra-rack electrical switching and inter-rack dynamic optical switching. This is not about mixing all manufacturers' GPUs into the same machine, but rather chips, servers, and optical networks beginning to divide labor and collaborate.
Figure 4 | The Future of Interconnects is More Likely to Be Layered: Short Distances Mainly Electrical, Cross-Rack and Larger Scales Gradually Increasing the Proportion of Optics.
Note: Layering is a conceptual summary; specific solutions vary by manufacturer.
V. Beyond Just GPGPUs: Domestic Compute Begins to Diverge
SuperNodes organize more chips at the system level. Other manufacturers have changed their entry points: starting from storage location, compute arrays, and workload specialization to reduce data movement, improve utilization, and use limited transistors for more matching tasks.
Near-Memory Computing: Tackling the Memory Wall First. Orient Computing, led by Professor Wei Shaojun, adopts the domestic 14nm process. The DF1000 uses wafer-level hybrid bonding to 3D stack compute and storage, announcing BF16 compute of 520 TFLOPS and on-chip storage bandwidth of 6.4 TB/s, paired with the TY64 64-card training/inference platform. The route logic is clear: shorten the movement distance. The costs are also clear: 3D packaging, heat dissipation, yield, and software adaptation are all hard constraints. Additionally, public materials for TY64 use standard Ethernet and do not yet possess the capability for a unified addressing ultra-large Scale-up domain.
Different Architectures, the Same Question: How to Increase "Useful Work". Tsingmicro follows the reconfigurable (CGRA) route: the mass-produced product is TX81, and the WAIC debut is the next-generation TX82 3D prototype, paired with the RAISA software stack adapting to frameworks like PyTorch, vLLM, and SGLang. Its REX81 SuperNode is composed of directly connected reconfigurable chips, and the company claims a single cluster can reach up to 4,096 chips. Kunlunxin's P800 uses self-developed XPU Link to build a single-cabinet 32/64-card full interconnect, and then scales out via IB or RoCE. The architectures differ, but all are answering the same question: the transistors are already there, how to make them spend more time doing effective compute rather than waiting for data.
Specialization: Narrowing the Battlefield. SOPHGO's BM1690 targets large model training and inference, supporting precisions like BF16, FP16, FP8, and INT8. Sunrise focuses on data center inference GPUs, with S2 and S3 advancing the engineering of large model and Agent inference. Specialization trades a narrower scope of application for throughput or TCO, but relies more on operator coverage, quantization precision, and tail latency performance under real traffic.
These routes are complementary to general GPUs in the short term, not replacements. Their significance lies in: domestic compute is moving from copying a single card to designing different systems for different bottlenecks. The divergence of routes itself is not the answer, but a signal that the industry has entered the stage of engineering trade-offs.
VI. Beyond the Hustle and Bustle, Domestic Compute Still Faces Four Hard Thresholds
Exhibition booths can be set up in four days, but compute systems must run continuously in customer data centers for months. What determines whether domestic SuperNodes can move from being able to be showcased to being able to be delivered are four mutually restricting thresholds.
Process and Energy Efficiency. Advanced nodes directly determine single-card performance, power consumption, and cabinet density. Huawei has publicly acknowledged the gap in domestic manufacturing, choosing to compensate with more chips and system architecture—the cost is a simultaneous increase in power supply, liquid cooling, data center space, and failure points. Compensation can expand available compute, but the single-card gap has not disappeared.
HBM and Interconnects. The US Department of Commerce BIS has listed HBM as a critical component for AI training and inference, and strengthened related export controls. VRAM capacity determines whether the model can fit, bandwidth determines whether compute units can be fed, and Scale-up interconnects determine whether multiple cards can collaborate—these three layers of bottlenecks overlap. Unified addressing, near-memory, and optical interconnects each alleviate a part, but no single solution can eliminate the costs of remote access, optoelectronic conversion, and data consistency for free.
Packaging and Delivery. 2.5D/3D Advanced Packaging must simultaneously handle large-size substrates, HBM stacking, thermal stress, and yield; SuperNodes further add switching chips, optical modules, power supply, liquid cooling, firmware, and maintenance. If any link is unstable, peak compute turns into downtime. Lighting up a prototype only shows it "can work"; batch delivery also needs to prove component consistency, maintainability, and supply chain cadence.
Software and Ecosystem. CANN, SAIL, MUSA, MXMACA, and RAISA are all supplementing frameworks, compilers, operator libraries, and model adaptation; Huawei claims to have completed the full open-sourcing of CANN and Mind series basic software by the end of 2025. But an ecosystem is not complete just by running one model—operator coverage, compilation quality, distributed communication, fault recovery, and version compatibility are all migration costs. Multiple domestic stacks being fragmented from each other remains a hidden tax for customers' large-scale deployment.
There is another frequently mentioned fallback: renting compute overseas. It can alleviate short-term gaps but is hard to become a stable alternative. The US Department of Commerce BIS clearly stated in its guidance on May 31, 2026: as long as the entity's headquarters or its ultimate parent company is located in Country Group D:5 or Macau, even if the entity itself is located overseas, exporting advanced computing items to it still requires a license, and this applies to all destinations outside the US; cross-border deployment also needs to add data compliance, network latency, model weight security, and engineering collaboration costs. Overseas resources are more like a bridge, not a long-term substitute for domestic compute.
Demand pressure is already evident. K3 hitting the capacity limit in three days at least indicates that hit frontier models may soon hit the ceiling of existing service capacity. The problem lies on the supply side: who can continuously deliver more effective tokens with limited chips, limited power, and limited budgets. The victory in the next stage will not be determined by the largest number of cards at the launch event, but by customer bills, long-term stability records, and expansion speed.
Table 3 | Four Hard Thresholds: System compensation has started, but every link still needs to undergo customer workload verification.
Conclusion: Models Can Be Open, But System Capabilities Must Still Be Delivered Layer by Layer
Back to Kimi K3. Moonshot plans to release the full weights before July 27. At that time, downloading the model won't be hard; the hard part is making 2.8 trillion parameters run stably under high concurrency and pushing the cost per token down to a level customers can accept.
K3 and domestic SuperNodes share the same industrial logic: the model side trades capabilities for sparse MoE and more efficient attention structures, while the hardware side trades effective compute for Scale-up, unified protocols, near-memory, reconfigurable architectures, and optical interconnects. Both sides are trading system efficiency for space. Looking further up, system competition is ultimately supply chain competition: wafer manufacturing, HBM, Advanced Packaging, and power/cooling must coordinate at the same cadence; if any link stalls, system scale is hard to translate into effective compute. The next generation of models will push systems engineering to the center of competition—this is the true narrative behind the WAIC 2026 exhibition booths.
From exhibition models to large-scale commercial use, the distance in between is not four months, but months of continuous throughput, latency, fault recovery, and cost per million tokens in customer data centers. Single cards are still chasing, but system competition has already begun. Rolling single cards is not the endgame; turning a bunch of cards into a deliverable supercomputer is the true cluster war for domestic compute.
Reference Sources and Methodology
Data in this article is as of July 2026. Citations prioritize official corporate technical materials, regulatory filings, official government and conference sources, and overseas mainstream media such as AP/Reuters, as well as overseas independent evaluations; domestic self-media are only used for discovering leads and are not the sole basis for key technical conclusions. The scale and peak performance announced by manufacturers belong to company statements. Launches, exhibition models, prototypes, customer tests, and batch deliveries are strictly distinguished; different precisions, sparsity, and test conditions are not directly compared horizontally. The training and online inference hardware for Kimi K3 have not been disclosed, and this article does not infer its use of Ascend or any specific domestic chip.
Reference Sources:
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[2]AP News | Moonshot Suspends New Subscriptions Due to Compute Capacity (2026-07-20)
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[14]Enflame SSE Materials / Iluvatar CoreX HKEX Materials | ESL64 and Tiangai 300
[15]ZTE Official / Lightelligence HKEX Materials | OEX, dOCS, and LightSphere
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[17]Tsingmicro / Kunlunxin | REX81 and P800 SuperNodes
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