Author: Peng Cheng
As 2026 draws to a close, the narrative tone of domestic AI chips has undergone a critical shift. In recent years, the industry repeatedly asked, "Can it be used?" and "Is it safe to use?" Now, the questions have changed to "Is it worth using?" and whether next-generation large models dare to bet on them.
The change first occurred on the inference side, but the true watershed moment appeared on the training side. Positive signals emerged almost simultaneously from both routes, pointing to the same judgment: domestic AI chips are no longer just alternative options under the shadow of sanctions; they are beginning to enter the core scenarios of frontline computing power demand.
01、Inference Side: From "Running" to "Outperforming H200"
Inference is the field where domestic chips first gained a foothold. Large model deployment has relatively higher tolerance for ecosystem migration, and the fragmentation of inference scenarios has left room for multiple parallel routes. From 2022 to 2025, US semiconductor export controls against China were tightened layer by layer. In April 2025, the US further restricted controls, forcing NVIDIA to halt sales of its China-specific H20 chip, resulting in approximately CNY 30 billion (USD 4.5 billion) in inventory losses and USD 8 billion in potential revenue losses. For the past three years, the H200 had been barred from the Chinese market; now, domestic AI chips have finally reached the H200 specification level.
First was MetaX's XiYun C600. This chip features 144GB of HBM3e memory, exceeding NVIDIA H200's 141GB specification. Mass production began in May 2026, and it was selected as the "first high-performance GPU built on a fully domestic supply chain," achieving a closed-loop domestic supply chain from design and manufacturing to packaging and software stack. While surpassing the memory capacity benchmark may seem like just a number on paper, for current top-tier large model training and inference, memory capacity is the hard limit for accommodating model parameters and context. Crossing the 141GB line means that for the first time, domestic GPUs are no longer lagging behind in flagship-level hardware specifications.
Then came Iluvatar CoreX's TianGai 300 released in July. Based on the Tianshu architecture, the TianGai 300 features new-generation Tensor Cores and Vector Cores, providing stronger computing capabilities and supporting various precision formats including FP4, FP8, BF16, and FP16, with 144GB of memory. Third-party tests showed that under typical prefill-decode separated deployment, the TianGai 300 achieved an overall end-to-end throughput per card equivalent to 1.05 times that of NVIDIA H200. In 64K long-context scenarios, Attention performance also reached 1.05 times that of H200. Multimodal generation inference throughput increased by approximately 2%-5%, and recommendation inference throughput in online businesses such as search, advertising, and recommendations rose by 21%. This is not a comparison of theoretical peak values on paper, but a comparison of actual output capabilities across the entire inference chain under specific model and deployment conditions. It is also the first general-purpose GPU in China to achieve measured performance levels comparable to the H200.
More new products surpassing the H200 are emerging. Biren Technology's next-generation GPU recently powered up successfully and is about to enter mass production. Sources indicate that this new product is based on domestic processes and will outperform NVIDIA H200. Biren Technology had already clearly advanced its BR20X series based on a new generation architecture earlier this year. The BR20X series natively supports broader data formats such as FP8 and FP4, equipped with larger memory and higher interconnect bandwidth, aiming to provide stronger computing power for cloud training and inference scenarios. After the BR20X, Biren plans the BR30X for cloud training and inference.
DF Compute will launch the DF2000 in Q4 of this year, achieving a memory access bandwidth of 15 TB/s and 1000 TFLOPS@BF16, with performance parameters comprehensively surpassing NVIDIA H200. In Q4 2027, the DF3000 will be launched, reaching a memory access bandwidth of 20 TB/s and 2000 TFLOPS@BF16, doubling the performance of the DF2000 and targeting NVIDIA B300.
The faster progress on the inference side is essentially because the commercial logic has completed its loop. IDC data shows that in the first half of 2026, NVIDIA's share in China's data center AI chip market dropped to 34%, with shipments declining 44% year-on-year; Huawei Ascend followed closely with a 28% share, narrowing the gap to just 6 percentage points. Among the 11 Chinese chip companies tracked by IDC, 9 saw year-on-year growth in shipments. The scaled verification on the inference side injected the scarcest resource into the industry: confidence.
02、Training Side: Domestic Chips Step to the Doorstep of Mainstream LLM Pre-training for the First Time
The overtaking on the inference side is a quantitative change; the breakthrough on the training side is a qualitative leap.
On November 3, 2026, reports indicated that DeepSeek's next-generation large model, DeepSeek V5, plans to conduct pre-training based on Ascend chips. Previously, Ascend's role in the DeepSeek system was limited to inference. V5 will be the first large model natively relying on Ascend for training, with core training computing power directed towards Ascend 950, and the project timeline pointing to implementation next year. Both parties completed extensive underlying operator adaptation and custom development during the V4 stage. For operators exclusive to DeepSeek models, Ascend initiated custom optimization during the V4 stage, opening technical channels for full-scale migration to Ascend training for V5. Actually, as early as late September this year, DeepSeek open-sourced infrastructure components for the Ascend computing platform, including TileLang compilation tools, computation libraries, and distributed communication libraries, corresponding one-to-one with previously open-source components for NVIDIA platforms. DeepSeek explicitly stated that every TileLang operator used in its training has a corresponding high-performance implementation on Ascend. Systematic alignment at the operator layer is the true engineering foundation for training migration. Without this step, the V5 pre-training plan would be impossible.
The loosening on the training side did not stop with DeepSeek alone; signs had appeared earlier. In January 2026, Zhipu AI released GLM-Image, the first top-tier multimodal model trained entirely on Huawei Ascend chips, completing the full loop from data preprocessing to large-scale training using Ascend Atlas 800T A2 devices and the MindSpore framework. On January 14, Zhipu jointly open-sourced the model with Huawei. Within 24 hours of release, it topped the global AI open-source community Hugging Face Trending list. This is also the first SOTA multimodal model achieving full-process training relying on domestic chips.
Other domestic AI chips have also made breakthroughs on the training side. On January 13, Moore Threads and Beijing Academy of Artificial Intelligence (BAAI) achieved a breakthrough. Relying on the MTT S5000 thousand-card intelligent computing cluster and the FlagOS-Robo framework, they successfully completed the full-process training of BAAI's self-developed embodied brain model RoboBrain 2.5. This achievement initially verified the usability and efficiency of domestic computing clusters in embodied intelligence large model training, marking that domestic AI infrastructure possesses the capability to handle complex multimodal tasks. Furthermore, combined with comprehensive training suites and leading training optimization and reinforcement learning technologies, the Ku'e Intelligent Computing Cluster based on Moore Threads' full-function GPUs has achieved breakthroughs in key dimensions. For example, in terms of high scalability, linear scaling efficiency remains as high as 95% as cluster training scale increases; in terms of high precision, training accuracy matches international mainstream computing cards, with highly consistent training loss curves; in terms of high stability, the cluster supports checkpoint resumption, with effective training time accounting for over 90%. Based on this, the Moore Threads Ku'e Intelligent Computing Cluster has completed multiple practices of "training domestic models with domestic chips," including training the MoE-236B base model from scratch and achieving full-stack native training of Peking University's 5D world model EvoPhys-World, fully verifying the closed-loop capability of domestic chips in ultra-large-scale, ultra-long continuous stable training.
Domestic chips on the training end are moving from peripheral links such as post-training and fine-tuning to the core link of mainstream large model pre-training, which had never truly opened before. Of course, the cost of ecosystem migration on the training side remains the variable determining the ceiling. Although the CANN software stack achieved comprehensive open source and openness in 2026, compatible with mainstream ecosystems such as PyTorch, vLLM, and TileLang, and MindSpore iterated to support MXFP8 low-precision training for Ascend 950, the developer inertia and operator richness accumulated by CUDA over more than a decade cannot be erased overnight. Whether V5's pre-training can run through as scheduled will be the first true "major exam" for domestic training chips.
03、Behind the Breakthrough: Not Just Single-Point Progress
If one only looks at this counterattack at the chip level, more important things will be missed. These single-point breakthroughs densely appearing in the same time window are driven by structural changes underneath, which are the true keys.
The completeness of the industrial chain is visibly rising. An AI chip involves seven links from blueprint to landing: design, manufacturing, advanced packaging, equipment materials, EDA, and storage. China has formed considerable combat capabilities in five links: chip design, mature and some advanced process foundries, advanced packaging, NAND flash, and DRAM memory. IP licensing, lithography machines, high-end EDA, and HBM remain weaknesses, but the nature of these weaknesses is shifting from "completely blank" to "having roadmaps, verification loops, and mass production schedules." SJ Semiconductor has become the top enterprise in mainland China by 2.5D revenue scale, with a market share of approximately 85%. Additionally, SJ Semiconductor continues to enrich and improve technology platforms such as 3D Integration (3DIC) and 3D Packaging, aiming for breakthroughs in cutting-edge key technical fields of integrated circuit manufacturing. CXMT's global DRAM share rose from 4% in Q2 2025 to around 10% in Q2 2026, with the fifth-generation DRAM platform achieving mass production. As the foundations of manufacturing, packaging, and storage rise simultaneously, breakthroughs on the chip design end have replicable landing points.
Super nodes turn "single-card gaps" into "system problems." When single-card processes cannot catch up with TSMC and NVIDIA in the short term, domestic computing power chooses a more realistic path: boosting the effective computing power of multi-card clusters through high-speed interconnection and system-level engineering. Over 750 sets of Ascend 384 super nodes have been deployed, and large-scale supply of 950DT super nodes is targeted for the end of this year or early next year; Iluvatar CoreX IXL144 enters training and high-concurrency inference scenarios with a density of 144 cards and 10.1TB of memory per rack. The maturity of super nodes means the competitive unit for domestic chips upgrades from "one chip" to "a deliverable computing power system," which is the engineering prerequisite for the training side to undertake large model pre-training tasks.
Talent and capital are accelerating aggregation in the same direction. A few years ago, the predicament of domestic AI chips was largely a human resource predicament: few people understood architecture, even fewer understood Chiplet and HBM advanced packaging, and composite roles capable of bridging hardware and AI software stacks were nearly nonexistent. Now, Enflame offers annual packages up to CNY 1.8 million for AI chip architects specializing in Chiplet/D2D directions. "Advanced Packaging Design Engineer" and "Chip Packaging Process Engineer" have become standard options in recruitment lists for Moore Threads and Cambricon. Although high-end talent in some fields remains scarce, scarcity itself indicates real demand and industrial expansion, rather than indifference. Capital inflows are equally dense: Morchip AI completed nearly CNY 2 billion in financing within five months; MicroNuclearCore accumulated CNY 3 billion in financing within six months; DF Compute's post-A+ round valuation exceeded CNY 12.2 billion. Money and talent are flowing in the same direction, which is the most intuitive manifestation of the industry entering the construction phase from the exploration phase.
04、Conclusion
Looking at the performance overtaking on the inference side, the pre-training breakthrough on the training side, the vertical completion of the industrial chain, the systemic maturity of super nodes, and the accelerated convergence of talent and capital together, this round of breakthroughs for domestic AI chips does not signify a victory of comprehensive leadership. The gap in HBM remains obvious, the shortcomings in lithography machines and high-end EDA cannot be filled in two or three years, and the inertia of the CUDA ecosystem has far from dissipated. However, domestic chips have transformed from substitutes requiring care and tolerance into technical options that frontline large model companies can place in their core training roadmaps.